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Intel and the U.S. Defense Advanced Research Projects Agency (DARPA) today announced a three-year partnership to advance the development of domestically manufactured structured Application Specific Integrated Circuit (ASIC) platforms. The Structured Array Hardware for Automatically Realized Applications (SAHARA) partnership enables the design of custom chips that include state-of-the-art security countermeasure technologies. A reliable, secure, domestic source of leading-edge semiconductors remains critical to the U.S.
"We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it's all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel's advanced 10 nm semiconductor process," said José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group.
As the sole U.S.-based advanced semiconductor manufacturer, Intel promotes supply-chain security by utilizing facilities within the U.S. to manufacture, assemble and test custom chips for the SAHARA partnership.
"Structured ASICs have advantages over FPGAs that are widely used in many Department of Defense applications. In partnering with Intel on the SAHARA program, DARPA aims to transform currently fielded as well as future capabilities into structured ASIC implementations with significantly higher performance and lower power consumption," said Serge Leef, a program manager in DARPA's Microsystems Technology Office. "SAHARA aims to dramatically shorten the ASIC design process through automation while adding unique security features to support manufacturing of the resulting silicon in zero-trust environments. Additionally, Intel will establish domestic manufacturing capabilities for the structured ASICs on their 10 nm process."
In collaboration with the University of Florida, Texas A&M and University of Maryland, Intel will develop security countermeasure technologies that enhance protection of data and intellectual property from reverse engineering and counterfeiting. University teams will use rigorous verification, validation and new attack strategies to test the security of these chips. The security countermeasure technologies will be integrated into Intel's structured ASIC design flow.
Intel will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. Intel will manufacture these chips using its 10 nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.
Intel eASIC devices are structured ASICs, an intermediary technology between field-programmable gate arrays (FPGAs) and standard-cell ASICs. These devices provide lower unit-cost and run on lower power compared with FPGAs and provide a faster time to market and lower non-recurring engineering cost compared with standard-cell ASICs.
View at TechPowerUp Main Site
"We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it's all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel's advanced 10 nm semiconductor process," said José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group.
As the sole U.S.-based advanced semiconductor manufacturer, Intel promotes supply-chain security by utilizing facilities within the U.S. to manufacture, assemble and test custom chips for the SAHARA partnership.
"Structured ASICs have advantages over FPGAs that are widely used in many Department of Defense applications. In partnering with Intel on the SAHARA program, DARPA aims to transform currently fielded as well as future capabilities into structured ASIC implementations with significantly higher performance and lower power consumption," said Serge Leef, a program manager in DARPA's Microsystems Technology Office. "SAHARA aims to dramatically shorten the ASIC design process through automation while adding unique security features to support manufacturing of the resulting silicon in zero-trust environments. Additionally, Intel will establish domestic manufacturing capabilities for the structured ASICs on their 10 nm process."
In collaboration with the University of Florida, Texas A&M and University of Maryland, Intel will develop security countermeasure technologies that enhance protection of data and intellectual property from reverse engineering and counterfeiting. University teams will use rigorous verification, validation and new attack strategies to test the security of these chips. The security countermeasure technologies will be integrated into Intel's structured ASIC design flow.
Intel will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. Intel will manufacture these chips using its 10 nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.
Intel eASIC devices are structured ASICs, an intermediary technology between field-programmable gate arrays (FPGAs) and standard-cell ASICs. These devices provide lower unit-cost and run on lower power compared with FPGAs and provide a faster time to market and lower non-recurring engineering cost compared with standard-cell ASICs.
View at TechPowerUp Main Site
