Western Digital May Introduce Penta Layer Cell (PLC) NAND by 2025

[Tomorrow]

15% is lower than i expected actually. Even from Intel's own sales. Maxx is speaking like 75% or more of Intel's volume is QLC and they have sold hundreds of millions of them.
I guess my point is that QLC has not achieved significant market share and the progress to more bits per cell is slowing down more and more with WD/Kioxia for example not expecting PLC before 2025/2026. Intel is more optimistic but i think we have all seen what Intel's optimism in roadmaps looks like (10nm in 2015, reality in 2020, desktop/server in 2021).

 

[Wirko]

Check my image just above. It's scary, but not as bad as you think thanks to some innovative techniques.

Yes, it is scary. May I ask you, as you probably have the calculations at hand: how many electrons are stored in the gate per voltage step in QLC or PLC?

 

[Maxx]

15% is lower than i expected actually. Even from Intel's own sales. Maxx is speaking like 75% or more of Intel's volume is QLC and they have sold hundreds of millions of them.
I guess my point is that QLC has not achieved significant market share and the progress to more bits per cell is slowing down more and more with WD/Kioxia for example not expecting PLC before 2025/2026. Intel is more optimistic but i think we have all seen what Intel's optimism in roadmaps looks like (10nm in 2015, reality in 2020, desktop/server in 2021).

I was not speaking like that at all. I'm saying the only real QLC manufacturer on the market still managed 10 million QLC drives by Feb 2020. The time frame was always 2024+, which has been extended to 2025 due to the pandemic among other things (even though the need for it has increased through server requirements, the production and supply chains are lagging). Again, that combination is one reason it's not huge in the consumer space yet. Obviously Feb 2020 was before the pandemic. Nevertheless, by the end of 2020 Intel was already suggesting PLC for the future themselves (using floating gate, as Kioxia likely will with split-gate) but for QLC to overtake in bits by 2025, but again this is all available from numerous storage conferences including ISSCC this year. Further, Intel and others are already stating that SSDs will overtake HDDs in TCO by as early as 2022. All this talk in this thread by supposed experts in enterprise who don't even follow basic trends...including the move towards ZNS which mitigates so many shortcomings. But there are other areas of improvements to be had, some of which I linked here, like IBM's AI for QLC.

Roadmaps are always optimistic, that doesn't mean QLC is going to disappear. It doesn't mean TLC will reign in enterprise and PLC will succeed QLC before QLC reaches its peak. Which is one argument in this thread - that QLC has somehow failed. It hasn't, the time frame has shifted little since conferences in 2019 and in fact 2018 for that matter. PLC in 2025 (WD) or 2026 (TechInsights) does not mean penetration of any sort, it just means the beginning of the tech appearing. It takes years to refine and make it cost-effective. But some in here are acting like they just pile on more layers and call it a day. On the contrary, there's constant improvements in technology that I regularly cover (in technical detail) on my discord and as I said earlier, layers are no substitute for bits/cell (which again is why 3D MLC is basically nonexistent). At the end of the day, though, NAND is a junk memory, but its replacement by memristor/PCM in most areas is not feasible. The move from SLC to PLC is not exactly linear, don't mistake my thoughts for that - SLC still has a place in SCM to some extent - but clearly enterprise is moving towards QLC heavily.

The other vendors are behind in their QLC offering and are not as far in that ramp up but it's definitely happening.

Everybody I've spoken to the industry is pretty gung ho about QLC. Doesn't mean they're right, but the idea that QLC is pie-in-the-sky is ludicrous. One element people tend to forget is TCO - total cost of ownership - where SSDs will be outpacing HDDs sooner rather than later. For the record I've written white papers on several of these subjects within the last year for an enterprise/DC SSD manufacturer and I pulled data from many analysts, but I don't really see the point of going through all of that as the linked article supports me directly: the "transition" from QLC to PLC "will be slower." It takes time to mature.

Yes, it is scary. May I ask you, as you probably have the calculations at hand: how many electrons are stored in the gate per voltage step in QLC or PLC?

Depends largely on architecture, but generally speaking 3D FG has up to an order-of-magnitude more electrons per charge as the smallest planar. Planar was getting down to <100 electrons which was about an order-of-magnitude larger than tolerance (but only saw TLC, not QLC/PLC). I actually haven't done the full calculations but OLC is feasible (using napkin math in my head plus split-gate and other architectural improvements as noted in TI, but that would possibly be the limit).

 

[theeldest]

Yes, it is scary. May I ask you, as you probably have the calculations at hand: how many electrons are stored in the gate per voltage step in QLC or PLC?

Electrons per cell isn't tied to TLC vs QLC. Here's a bit from Anandtech back when Intel & Micron introduced their first 32-layer NAND: https://www.anandtech.com/show/9114/intelmicron-share-additional-details-of-their-3d-nand

The quick bits:

The slide Intel and Micron shared shows that their 3D NAND will have roughly the same number of electrons as their 50nm process did (or actually slightly more), which is over a tenfold improvement compared to the latest 16nm node.

Last I saw was 10 - 100 electrons for small planar cells and "thousands" for the first 3D nodes.

 

[jimmyxxx]

I'm not an expert in microelectronics, but I know a thing or two about data transmission and signal modulation and encoding. The issue of incrementing the bits per cell looks more or less like expanding the number of bits in a constellation. The higher the bit count for the constellation, means a more complex hardware at the receiver end to discern between one message or another. I guess there would be a point where it would make no sense to continue growing the bits per cell until the endurance problem is fixed.

 

[Maxx]

Last I saw was 10 - 100 electrons for small planar cells and "thousands" for the first 3D nodes.

Yep, it was sub-100 for planar and current 3D is up to an order-of-magnitude more (as I stated above). Tolerance back then was ~10 electrons (so 8 states, a la TLC, was feasible with planar, most obviously since we had planar TLC). So base 3D NAND can handle HLC (64 states) as-is, but once you add in split-gate and other technological advances (which can improve effective cell size and tolerance) it can get out to about OCL (256 states). I don't want to speculate too much though, but PLC with current tech would still have significantly better P/E than QLC was originally modeled for (100-150, when it's actually 1000-1500 with Intel). But we would likely want a better basis for HLC.

I'm not an expert in microelectronics, but I know a thing or two about data transmission and signal modulation and encoding. The issue of incrementing the bits per cell looks more or less like expanding the number of bits in a constellation. The higher the bit count for the constellation, means a more complex hardware at the receiver end to discern between one message or another. I guess there would be a point where it would make no sense to continue growing the bits per cell until the endurance problem is fixed.

Right, you have voltage thresholds for each state that cover a range with a probability curve. These are more or less even so to discern states you have to essentially have a tolerance level equal to the total charge/voltage divided by the number of states. Not precisely so because one of the states is ER (erased), it's n-1 reference voltages. As an example, planar NAND hit ~100 electrons with a tolerance of 10 electrons which was sufficient to allow for 8-state TLC (3-bit, 7 reference voltages). It's possible to improve effective cell size (and thus charge capacity) but it's basically down to physics, likewise it's possible to improve (lower) the tolerance threshold through a variety of techniques. Endurance as such is based on the RBER (raw bit error rate) as it will eventually exceed the ability to repair with ECC and then parity/RAID and of course sensitivity requirements increase with number of states for the same cell size.

You still have performance penalties over time as ECC and parity add latency. This includes write performance because you have narrower thresholds which require finer programming and part of the program sequence is read verification for the values.