Latest HWiNFO Update Adds Suport for XMP 3.0 on DDR5, Among Other Features

[Raevenlord]

The release notes for the latest version of famous system utility HWiNFO have spilled the beans on an update to Intel's XMP. Currently at version 2.0, XMP (eXtreme Memory Profile) is a technology that allows the system-level BIOS to run DDR memory at speeds higher than those allowed by JEDEC, the governing specifications body for all things memory. It extends the performance profiles usually made available via SPD (Serial Presence Detect). An update to Intel's XMP (XMP 3.0) for DDR5 memory is referred to in the release notes for version 7.05 of the software. Not much more to look at here - it remains to be seen what changes are actually a part of XMP 3.0, and if any increased utility will be added to these profiles. Remember, however, that nor Intel nor AMD (via its A-XMP implementation) enable warranty coverage should XMP be enabled in your system.

Other relevant updates for the application include advanced early support for Zen 4 systems (looking at you, AMD), as well as per-core temperature monitoring for Zen-based CPUs. There are other additions to the supported hardware, which you can find in the screenshot below.



View at TechPowerUp Main Site

 

[kayjay010101]

"per-core temperature monitoring for Zen-based CPUs" means just Zen 1 CPUs or all Zen-based CPUs?

 

[Raevenlord]

"per-core temperature monitoring for Zen-based CPUs" means just Zen 1 CPUs or all Zen-based CPUs?

Zen-based implies all Zen designs.

 

[AnarchoPrimitiv]

Will DDR5 provide a subjectively noticeable performance improvement for current CPU and dGPU hardware? In other words, is dual channel 3200Mhz+ DDR4 a bottleneck for current mid-range and above CPUs and GPUs? Would a system with a 5600x and a 6700xt that's currently using 16GB+ of 3600Mhz CL16 memory be noticeably improved by using DDR5 5200Mhz memory? I'm honestly asking.

I realize it'll help with APUs (though I'd much rather see HBM2e, at least 4GB included in the APU that's usable as both VRAM and an L4 CPU cache) , especially the upcoming RDNA2 based ones, but for your a dGPU based system, will it produce gains that can be seen by the user?

 

[tabascosauz]

Will DDR5 provide a subjectively noticeable performance improvement for current CPU and dGPU hardware? In other words, is dual channel 3200Mhz+ DDR4 a bottleneck for current mid-range and above CPUs and GPUs? Would a system with a 5600x and a 6700xt that's currently using 16GB+ of 3600Mhz CL16 memory be noticeably improved by using DDR5 5200Mhz memory? I'm honestly asking.

I realize it'll help with APUs (though I'd much rather see HBM2e, at least 4GB included in the APU that's usable as both VRAM and an L4 CPU cache) , especially the upcoming RDNA2 based ones, but for your a dGPU based system, will it produce gains that can be seen by the user?

As long as AMD sticks with Infinity Fabric (although constantly improving), there should always be an emphasis on running fast+tight memory on Ryzen. Even more so with chiplets. Infinity Cache and 3D V-Cache should mitigate the need on both CPUs and APUs, but the need will still remain.

APUs might not care about timings (well, kinda a myth really, at the top end I can still claw back 25-50MHz lower iGPU core OC on just tRFC and tRTP alone) but the CPUs kinda do. All the DDR5 you'll find for the next little while will be JEDEC spec, so slow as molasses and pointless (think DDR4-2133 CL15 JEDEC vs your average DDR4-3600 CL16 kit). It's DDR3-2400 CL9 vs. DDR4-2133 CL15 all over again (granted, X99 memory controller was doodoo and contributed to the perception that early DDR4 was even worse than already was).

But even with our systems now the difference is negligible past 3600. Probably should focus more on running 2 ranks per channel (versus 2 single rank sticks) than anything, might actually feel the diff there in games.

as well as per-core temperature monitoring for Zen-based CPUs

This be something that has never been done in any software on Zen. Interesting. Pretty useful, I kinda wanna see exactly how Core 0 and 1 are behaving when >13W, as opposed to skewing the entire CCD1 average. I hope it doesn't break Snapshot Polling like AGESA 1200 did.

 

[kayjay010101]

Zen-based implies all Zen designs.

Indeed it does, I now have per-core temps on my 5950X with the newest beta. Crazy that it's taken this long if the sensors were there all along...

 

[Mussels]

Indeed it does, I now have per-core temps on my 5950X with the newest beta. Crazy that it's taken this long if the sensors were there all along...

well if no one knew how to read them, it couldnt be done

Looks good, and the core readings are much lower/what i expected all along, vs the inflated Tdie reading

 

[kayjay010101]

well if no one knew how to read them, it couldnt be done

Looks good, and the core readings are much lower/what i expected all along, vs the inflated Tdie reading

View attachment 205208

Well I assume AMD knew they were there, but never implemented the function to read them, even in their own software. Just kind of strange as it's something the community's been asking for for years
And yeah, they're surprisingly good temps. Tdie seems to always be 5-10C above the actual core temps, even under constant load.