That guy comment was pretty rude, but it's not full 3D but more 2.5D
3D chip is not there yet and not around the corner (if it ever come). Right now it's each die are in 2D. they can stack those and have TSV, but it remain that each layer is 2D. 3D will allow very complex transistor layout. It would help with propagation as you would be able to make denser logic with less space. But I am still not even sure we can make those in labs...
Anyway, that do not mean that this 3D cache isn't impressive. It's actually very impressive and only the beginning of die stacking. The next decade will be very interesting, trust me on that. This is only the beginning.
You're missing a lot bro.
Modern CPU's and GPU's are already 3D, there are many layers in the design. A regular modern CPU (14nm era) is already 13+ layers. The transistors and interconnects are present in multiple layers, like a tiny futuristic city.
3D NAND is a different process, while there are layers, but these are mostly films, and the nature of NAND make it very different than a modern CPU/GPU.
2.5D is when you put different silicon die over a silicon interposer, like how HBM memory is packaged, because HBM memory have very high density interconnect that normal packaging substrate is not enough, modern packaging material is called organic substrate, it is used to connect the actual die to the package pins (with a socketed or non-socketed package like BGA). It's okay for the organic interposer to be used in this case because you have a limited number of traces per mm. With HBM, you need much more traces per mm that organic substrate can't handle it, you need a silicon substrate which is made just like how a normal silicon die is made which will have traces between the GPU/CPU to the HBM memory and traces between them to the organic substrate/interposer below it to connect to the PCB board.
There are two kinds of silicon interposers here, Passive and Active. Passive interposers have no functionality beside connecting the dies and the substrate together. Active interposers can have an actual logic in it, such as basic IO logic, Cache, power management or some other basic functional circuitry.
AMD has used passive interposers 2.5D packaging for a while, and now both NV and Intel are also uses it. Intel announced plans on using Active interposers in future plans (making the interposer with some basic IO functionality), but they don't have any product yet.
3D is similar to 2.5D in the term is that two silicon dies are on top of each other. But the different is that at least the base silicon die is a totally functional die. Here we have just that, the base die is the actual CPU die.
3D die stacking has been in the work for years but the main issues are interconnect and heat which made the tech unusable for high-end designs. TSV has been in use for years (mainly in 3D NAND) and AMD has used it in this proven technology with a twist, TSV is usually done with solder, but AMD used copper instead which helps more with the heat problem. To add another solution, they used a smaller top silicon die that only covers the cache in the base die, cache doesn't produce that much heat to begin with, so the left the actual cores exposed, they only need to put some dummy silicon over the CPU core to make the V height equal and get even pressure and contact on the whole Core die. Silicon is a good heat conductor as well (not as good as copper, but slightly better than aluminium).
same deal with 2019 2700X vs 2019 3700X. Moral of the story, don't ever trust AMD with your money on launch day (or for the next month at the minimum), because YOU are AMD testing department's unpaid interns
