Raptor Cove cores replace Golden Cove : +IPC, +200Mhz boost, larger L2 cache, DLVR for higher performance/lower power, faster official DDR5 support (5600), and more E cores - at least that is the current leak.
The efficiency cores (Gracemont) will be the same uArch, just more of them.
Intel DLVR can provide up to 7% more performance with 21% lower voltage An interesting thread has recently appeared on Reddit. It covers the concept of the Digital Linear Voltage Regulator (DLVR) which might be used with the upcoming Intel Raptor Lake CPU series. Intel Raptor Lake Digital...
videocardz.com
Intel's Raptor Lake-S Desktop CPUs 13th Gen Core family & feature up to cores based on the Raptor Cove core architecture have leaked.
wccftech.com
DLVR and the doubling of number of E cores makes this worth waiting for. I think AMD will have a hard time convincing me to transition to AM4 or TR based on this. I wish AMD would've done more with TR a few years back at this point it's probably too little too late unless they absolutely surprise me with something bold and much more cost effective than TR has been to this point. I don't think AM4 has enough left in the tank however not until a die shrink and they'll have moved away from DDR4 by that point in time I feel which I'm already set on reusing on my next build.
The DLVR is great and doubling E cores will absolutely help not just multi-core performance further, but it can help with efficiency in turn with more CPU multipliers to scale. I'm telling you now though Intel could use a mid-core die chip with 2C 1HT that sits between a P core and E core and has AVX512 with a frequency between the two. That is one of the next logical steps to this scaling design. Intel could drop 4 P cores and insert 8 of those types of cores in place of them and further boost efficiency and multi-core performance. You'd get more reliable performance at the same time in workloads that do actually depend on AVX512 or ones that do show some upside to HT.
Instead of a 12900K Intel could do something more akin to the following 4P cores 1C 2HT AVX512, 8M cores 2C 1HT AVX512, 16E cores 16C 0HT no AXV512. The P cores would be highest frequency, M cores mid frequency, and E cores lowest frequency. It would be a good practical blend and continuation. I think later on if they were to add a 4th lower frequency core they could insert HT, but still drop the AVX512. I think it would be good for highly parallel I/O workloads that still benefit from HT yet don't require a lot of frequency or AVX512 at the same time.
One more thing Intel could do with bigLITTLE is start doing the same with the iGPU they should create a bigLITTLE iGPU. Some people would probably cringe at that, but I think it would be quite good potentially and particularly well suited to get higher GPU performance at higher resolutions which is where iGPU's struggle the most. It wouldn't be too dissimilar to what Lucid Hydra was trying to do, but with all the janky latency of attempting it while bottle-necked by the NB latency that obviously Intel doesn't have to worry about integrated into the CPU itself.
I think this is a spot where Raja could redeem his reputation over VEGA if it went well. Think of it this way too a scene renders and the the far distance LOD details start to pop in a little bit more slowly common enough scenario right!!? Slight delay and the end user can live with it even if it isn't quite perfectly ideal. Seems like a perfect example of where to apply a LITTLE iGPU core to render the far distance scene detail a bit less aggressively while the closer more near draw distance the big core tackles. It's a good way to handle lighting and shading as well let the LITTLE cores handle of the weaker of the two variable rate lighting or shading in the far LOD distance while the more capable one handles the closer details.
That might all be true, but I was simply referring to the figures presented in this review. Allegedly, the single threaded power efficiency should be based on the SuperPI test. In this test, the P-Cores are much more performant than the E-Cores. The power draw in this test is about the same for both P and E-Cores. Based on those results the P-Cores should be a lot more efficient in this particular test, yet, the figure of power efficiency for SuperPI shows opposite result. It does not make sense to me.
4 to 1 ratio give or take within the same die space area roughly makes perfect sense to me. Yeah the E cores die for die when comparing 1C to 1C aren't going to be as efficient, but why would anyone measure it that way in the first place!!?
Also you can reduce the multipliers and frequency on the E cores and make them more efficient or less efficient in a comparison like that provided you aren't measuring IPC efficiency at 1C at the same clock frequency between both you can make the E cores more efficient or less efficient in relationship to the P cores and vice verse. It's just like the music saying goes it's not the instrument it's how you use it. I mean 18% higher power draw for 47.8% higher peak performance per die space area says enough about the E cores efficiency and performance.
How is that tough to grasp really that's a good figure less than 1/4 additional power draw for about 1/2 more performance within the same die space yeah not bad and especially considering how voltage is squared. The whole point is not needlessly jacking up frequency too drastically along with voltage along with all the added heat that further makes you jack up the voltage and is a losing battle that won't scale linearly it gets progressively more difficult and inefficient look at the P cores and overclocking them it's like rolling coal ffs it ain't pretty how much power draw is required for a meager 100MHz higher frequency at that end of the spectrum.
They give the performance of a 3600X, while using more power.
These E-cores that specifically exist exclusively for one goal of power efficiency, are outdone by last gen budget products by the competition in both power consumption and performance.
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I like the concept. I like the goal.
But these are still power hungry monsters, and do not achieve what they pretend to be... they're just a method to pad the core count and multi threading results, without needing 500W CPU's.
They are neither low power, high performance, or energy efficient.
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How fair a comparison is this to draw however!? You're trying to compare a 129000K's E cores only to a 3300X and 3900X I mean show some integrity. You do realize you can drop the multipliers on the P cores to match the frequency on the E cores. You have to consider the die space area. You're pretty much comparing a damn 7nm dual P cores Pentium's die space against a 3300x and 3900x.
In terms of the die space occupied Intel could feasibly cram 40E cores roughly into a 12900K or 36E cores with a single P core. In fact Intel dropping the iGPU could insert 40E cores with 1P core or 44E cores with no P cores within the same chip space. The ring bus would probably be a complex matter far as that goes, but it's feasible if they wanted to put the R&D into making it happen.
Also the 129000K has PCIE 5.0 while those other chips are PCIE 4.0 plus DDR5 capable even though at this point DDR5 expensive for is mediocre upside and not something I'd entertain myself, but given some time and cost reduction and the tables will turn these chips will still be around in a year or two and probably discounted a bit so down the road comparing both should little a little different narrative wise.
Alder Lake and bigLITTLE now is similar to when Ryzen was first introduced. It isn't perfect, but give it 2 or 3 more iterations and bigLITTLE will have improved by so much more. I've already talked about pretty decent number of ways they can improve upon it and I'm sure Intel is thinking about even more it's quite clear it's here to stay and will continue to evolve. We've moved beyond simply multiplying core count further towards additional cores with different performance characteristics and considerations it's progress.
Not everyone is happy about that, but it's logical path of progression when chips are thermally limited it's the only way around the problem pacing the heat output is the key to more performance on demand. This is exactly what Intel should've done in this scenario and needed to do and if anything should have been more aggressively pursuing it. I wish that Intel would've just had 1 or 2 P cores on the 12900K and the rest E cores.
As I've been saying a mid core is something I see as a needed stepping stone to make the whole thing smoother a 2C 1HT mid frequency chip die cluster that also has AVX512. Slightly slower P core, but twice as many with half the HT while retaining AVX512 and lowering frequency a nudge.
The quirks and I think those can be worked out in due time pretty readily maybe not as well with Alder Lake, but once a mid core gets introduced I'm convinced it will be a smooth criminal operation by the Intel monopoly.
