AMD EPYC "Genoa" Socket SP5 16-core Processor Prototype Pictured in the Flesh

[btarunr]

Here are some of the first real-world pictures of the next-generation AMD EPYC "Genoa" enterprise processors in the Socket SP5 package. The coaster-sized 6,080-pin SP5 package gives AMD's chip-designers fiberglass substrate real-estate to dial up CCD counts up to 12, resulting in up to 96 "Zen 4" CPU cores for "Genoa." Pictured below is a 16-core prototype with just two CCDs in place, as revealed by an X-ray shot. Socket SP5 gives "Genoa" some stellar I/O capabilities, including 24x 40-bit DDR5 channels (12-channel in the classical definition), and 128x PCI-Express Gen 5.0 lanes. AMD is expected to time its EPYC "Genoa" processor launch within 2022, to best compete with Intel's Xeon "Sapphire Rapids" processor launch. It will also launch a variant codenamed "Bergamo," based on "Zen 4c" CPU cores, with up to 128 cores to go around.



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[PilleniusMC]

That is very.... quadratic.

 

[Steevo]

That coaster size socket looks expensive

 

[DemonicRyzen666]

Will there be a WRX90/WRX100? for Threadripper pro version of this monstrosity? lol
going to be sad to see TRX40 get left behind.

 

[r00lz]

I can imagine 96 core/192 thread version from free space

 

[Deleted member 24505]

Yikes, that is a lot of connections, and a big boy CPU.

 

[kondamin]

"AM5 will be a long lasting socket" if they need 12 memory channels to feed 96 zen4 cores AM5 will be a 4 core system only by the end of it's life.

 

[Aquinus]

The coaster-sized 6,080-pin SP5 package

Socket SP5 gives "Genoa" some stellar I/O capabilities, including 24x 40-bit DDR5 channels (12-channel in the classical definition), and 128x PCI-Express Gen 5.0 lanes.

That's an absolutely insane amount of I/O. Who needs a PCIe switch when you have 128 lanes of PCIe 5.0. You need all of those memory channels to keep the PCIe lanes fed.

 

[Deleted member 24505]

That's an absolutely insane amount of I/O. Who needs a PCIe switch when you have 128 lanes of PCIe 5.0. You need all of those memory channels to keep the PCIe lanes fed.

Can run a ton of x4 PCIe 5 m.2

 

[AusWolf]

It looks like AMD got tired of "gluing" chiplets together to make one CPU. The new trend will be "gluing" CPUs together!