Possible GeForce RTX 4070 "Ada" Specs Hit the Rumor Mill

[btarunr]

Two sets of possible specifications of the upcoming performance-segment NVIDIA GeForce RTX 4070 "Ada" graphics card has hit the rumor-mill, according to kopite7kimi, a reliable source with NVIDIA leaks. The first set of specs sees the card feature 12 GB of 21 Gbps GDDR6X memory (possibly over a 192-bit wide memory bus), as many as 7,680 CUDA cores, a typical board power of 285 W, and an internal SKU code of "PG141-SKU340/341." It makes sense for 12 GB of memory across a 192-bit memory bus to be a logical choice for NVIDIA (as opposed to the previous-gen RTX 3070 with its 8 GB of 14 Gbps GDDR6 across 256-bit); as it allows the company to achieve a 50% memory size increase gen-over-gen, while reducing the number of memory chips on the card from 8 to 6 (by using six 16 Gbit GDDR6X chips).

The second set of specs doing rounds is the "PG141-SKU336/337," consisting of 7,168 CUDA cores, 10 GB of 21 Gbps GDDR6X memory across what we're assuming could be a 160-bit wide memory bus (five memory chips), and 250 W typical board power. The same source also claims that the SKU340/341 could have a performance target of over 11000 points in Time Spy Extreme, while the SKU336/337 could be designed with at least 10000 points in mind. It's quite possible that the second configuration is that of the RTX 3060 Ti-successor SKU. Given NVIDIA's top-down approach to product launches, we could expect performance-segment SKUs only toward the end of 2022, or early-2023.



View at TechPowerUp Main Site | Source

 

[Minus Infinity]

How the worm has turned. Nvidia reducing bus width, while AMD is increasing it for RDNA3. 7700XT is 256 bit, 7800XT 320 bit and 7900XT is 384 bit.

 

[TheDeeGee]

TDP of the 4000 series getting lower by the week

 

[Dirt Chip]

TDP of the 4000 series getting lower by the week

Give it another 4 month of leaks and rumors and you will see sub-zero consumption.
It will actually generate W just for using it...
Bye bye thermodynamics

 

[pavle]

Memory bus width shows how efficient an architecture is. NV has historically had better HSR (hidden surface removal) than ATi, so it doesn't need all that wide bus. They must really have an ace up their collective sleeve to pridefully give a x70 card only 160-bit bus. Or they just think that sticking 100MB of cache onto a chip will help it that much, which might not be so far fetched given they are a hybrid tile architecture since nvMaxwell...

 

[TheoneandonlyMrK]

Memory bus width shows how efficient an architecture is. NV has historically had better HSR (hidden surface removal) than ATi, so it doesn't need all that wide bus. They must really have an ace up their collective sleeve to pridefully give a x70 card only 160-bit bus. Or they just think that sticking 100MB of cache onto a chip will help it that much, which might not be so far fetched given they are a hybrid tile architecture since nvMaxwell... View attachment 259865

What do you mean by hybrid tile, these are, have been monolithic single die GPU and this isn't hopper or a derivative.

 

[ppn]

Some leaks were hinting 2x rops. 4070 could have 160 ROPs. 4080 224 and so on. to compensate for the bus. But better call it 4050Ti and 4060. cmon.

What do you mean by hybrid tile, these are, have been monolithic single die GPU and this isn't hopper or a derivative.

On NVIDIA's Tile-Based Rendering

 

[Candycrushsodasaga2]

Smaller bus means less power consumption (thanks to TSMC), and despite that it still looks like the 4070 can easily ace the 3090 ti...
i'm sure you can get even more out of it if you overclock it a bit, but power consumption would go up.
Hopefully the 4070 can beat the 7700xt, which has an even smaller 128bit bus right now, the red team is also trying to stuff more cores into their cards as well.

 

[TheoneandonlyMrK]

Some leaks were hinting 2x rops. 4070 could have 160 ROPs. 4080 224 and so on. to compensate for the bus. But better call it 4050Ti and 4060. cmon.

On NVIDIA's Tile-Based Rendering

Oh right, tile based rendering, he made it sound like a chip made of tile's.
Ty.

 

[ppn]

the red team is also trying to stuff more cores into their cards as well.

It's more complicated than that, Apparently AMD has started to count ALUs differently much like nvidia Ampere.

6600 XT 237 mm² 2048
7600 XT 203 mm² 4096 ALu everything esle the same 32MB 64 Rops 128 bit

See what they did there, 4096 new Shading Units = 2048 old Shading Units able to execute Int32 or float point shrinked to 6nm.

 

[john_]

shrinked to 6nm.

5nm. RDNA3 is 5nm, so maybe they can stuff more cores in less area.

 

[Vayra86]

285W is steep for an x70, and royally over what I want in my rig.

And that's the throttling FE version even.

 

[ppn]

5nm. RDNA3 is 5nm, so maybe they can stuff more cores in less area.

the entire NAVI33 is 6nm, the Memory tile on the NAVi32 and 31 is too.

so 7600 XT being 203 mm by 1,18 density improvement 7/6 nm = 239 mm is exactly the same thing as 6600 XT. Yeah, lo and behold RDNA3

 

[DeathtoGnomes]

Oh right, tile based rendering, he made it sound like a chip made of tile's.
Ty.

Well, they are, square chips are tiled onto the card.

You cant tile round chips.

 

[sepheronx]

Hopefully that 3090 I ordered doesn't arrive so I can get my money back for a 4070.

 

[pavle]

What do you mean by hybrid tile, these are, have been monolithic single die GPU and this isn't hopper or a derivative.

Tile based rendering. Do not get confused by all the tile talk Adios my dineros is spreading around.

285W is steep for an x70, and royally over what I want in my rig.

And that's the throttling FE version even.

No way - what about Amperage card, they're not exactly a good example; more like Fermi on styroids (intentional)?

 

[PapaTaipei]

My 1080ti has 352bit memory bus. Are we going backwards from now on?

 

[Dirt Chip]

The "not enough bit-bus-memory" is only secondary to the "not enough memory".

When combined, thay make the all mighty "not future proof" Doomsday weapon of GPU's.

 

[ModEl4]

Wasn't Kopite7kimi all 2022 supporting 420W for RTX 4080 and recently changed it to 340W?
A few days ago it gave power figures for AD106 based RTX 4060 (230W-240W) that will also fail.
Even by his performance claims you can deduct performance for all configs and if the power draw was what he was saying, i can imagine Jensen in stage at the announcement day detailing performance/W improvements and the audience:"are you f**king kidding me"?
He changed from time to time his wording from TBP, to power limit, to power draw etc but the fact is he was off regarding Ada Lovelace unless Nvidia saw the war and energy crisis and suddenly changed their plans, lol yes sure...

 

[Minus Infinity]

Smaller bus means less power consumption (thanks to TSMC), and despite that it still looks like the 4070 can easily ace the 3090 ti...
i'm sure you can get even more out of it if you overclock it a bit, but power consumption would go up.
Hopefully the 4070 can beat the 7700xt, which has an even smaller 128bit bus right now, the red team is also trying to stuff more cores into their cards as well.

What 7700XT right now! 7700XT is going to be 256 bit when released. Current 6700XT is not 128 bit even being 192 bit. 6600XT is 128 bit which is what the 4060 will now be and 4060 Ti will be 160 bit.

Also why hopefully should the 4070 beat the 7700XT? What a weird statement. Also I doubt the 4070 will easily beat the 3090Ti at all. It could be close and it could win but not by a lot. Let's see how it fairs at 4K with RT on. AMD's perforamnce dropped off at 4K due to the gimped bus widths despite large IC. 4070Ti should handily beat 3090Ti though.

 

[pavle]

It's not about bandwidth, it's how much you draw and per frame you want to draw as little as possible.

 

[PapaTaipei]

It's not about bandwidth, it's how much you draw and per frame you want to draw as little as possible.

Can you elaborate on this topic? It would be cool to have for once someone explaining this clearly.

 

[pavle]

Can you elaborate on this topic? It would be cool to have for once someone explaining this clearly.

Of course - here's a simple picture I draw that shows in [A] how 3D rendering works least efficient (draws everything, sorts later) and in [B] how it is works most efficient (doesn't draw what cannot be seen in the first place). If you make a 3D chip that does [B] most or all of the time, you need at least 2x less memory bandwidth, shows even more benefits in complex scenes.