My main question here is: what generation of PCIe will USB4 v2 enable? Is it PCIe4.0? 5.0? And how many lanes of PCIe bandwidth? Finally, we've heard that with PAM3 signaling, existing TB4 (and USB4 40 Gbps?) cables will be able to take advantage of the new data speeds, no problem. But what about existing TB4 controllers...will a firmware update enable them to pump data at faster than 40 Gbps? I doubt this: my thought is TB4 controllers are connected to the PCIe root complex at PCIe 3.0... foreclosing any opportunity for a speed bump via a firmware update.
Below is a drawing of current TB4 solution and expected TB5 solution with PAM 3. It could give an answer about anticipated PCIe standard used both for USB4 2.0 and TB5. It seems that PCIe switch will be Gen5 x4. It will link to four Gen5 lanes on Intel's CPU or AMD's CPU for USB4 2.0 solution. A few years later such PCIe switch could wire to chipset once those get PCIe 5.0 capability. Or sooner, if the PCIe switch wires to eight Gen 4 lanes on the chipset.
PCIe switch chip needs to be Gen5 x4. There are several reasons for that. It gives an access to 128 Gbps of data speed. If symmetrical solution is implemented (easier one), this total bandwidth could be distributed into two ports running at Gen4 x4 each, so that each port gets up to 64 Gbps of PCIe data to any peripherals, which would largely be Gen4 for years. As Thunderbolt 5/USB4 2.0 port will have 80 Gbps bandwidth in total in one direction, this makes sense.
TB5 port (80 Gbps) expected capabilities:
1. one DP 2.0 80 Gbps display or two DP 2.0 40 Gbps displays (4K/120 10-bit RGB panels) - if two such displays are daisy-chained, bandwidth of one port is saturated with DP data only
2. PCIe Gen4 x4 up to 64 Gbps, if no other traffic consumes more than 16 Gbps, such as DP monitor and/or USB device. PCIe data available bandwidth will be reduced if high-end monitor is connected, as display data get priority
3. USB 20+ Gbps (xHCI 1.2 or newer controller)
4. PD 3.1 up to 240W (TI most likely)
5. Networking - more than 10 GbE?
In this light, USB4 2.0 chip/port might have slightly less stringent obligatory features than TB5, such as one mandatory display instead of two, etc. But yes, USB4 2.0 should use PCIe 5.0 x4 on CPU link and minimum PCIe 4.0 x4 on port PHY.
Existing cables will not be able to use 80 Gbps speeds, as new chips are needed in cables to recognize and transmit all those standards that will be implemented. The same applies for HDMI and DP cables. Cables designed for older standards cannot miraculously use most of new features. For example, Intel designed TB redriver JHL5040D to work with 40 Gbps cables. This chip implements DP 2.0 UHBR10 traffic for 40 Gbps connections and USB 3.2 Gen 2x2 for 20 Gbps traffic. Such redriver cannot operate with 80 Gbps traffic, as it is not capable of supporting DP UHBR20 traffic. Nothing is known about tunnelling capabilities of this redriver.
You are right. Firmware update cannot bake in hardware capabilities. New IP solutions are needed.
