Samsung Develops GDDR6W Memory Standard: Double the Bandwidth and Density of GDDR6 Through Packaging Innovations

[chrcoluk]

I wonder if this will be leveraged for double the speed and capacity, or just leveraged for the currently planned speeds and capacities by using half the amount of chips, saving money but likely not passing that saving on to consumers...

The latter of course as SMR and QLC has proven.

 

[Punkenjoy]

I wasn't talking about RDNA3 using GDDR6W. I'm sorry if I gave that impression. I was just talking bandwidth in general.

I agree that each RDNA3 MCD has a 64-bit wide memory bus and it's difficult to fit more than 6 on a single package. However, future RDNA4 MCD can have 96-bit/128-bit wide memory bus. That's what GDDR6W is targeting anyway.



Moar bandwidth comes at an increased cost anyway. That's expected.

On another note, Nvidia would have benefitted a lot from something like this in 2020 with Ampere (in terms of VRAM size).

RTX 3080 came with 320-bit 19 GHz = 760 GB/sec bandwidth but only had 10 GB capacity.

Considering GDDR6 was at 14 GHz in Ampere, 448-bit 14 GHz = 784 GB/sec bandwidth with 14 GB VRAM size.

First, From the comments from AMD I wouldn't be surprised at all if NAVI 4x use the same MCD than Navi 3x (a bit like on Ryzen where they reuse the same I/O die for multiple generation).

You can view the Gamer Nexus Video on chiplets, AMD explain it pretty well. The design of the memory controller and other stuff is hard, take a lot of time and is boring for not so much gain anyway. The fact that they will be able to reuse it for the next gen will probably allow them to ship it earlier. If those MCD already support GDDR7 and cache stacking, I don't see why they would update it for next gen.

Again, a misconception of those chip are that they increase the bandwidth. They doesn't really, They increase the bandwidth per chip, but not per bus size. You could just put the double amount of chips on your board (like on both side) and you would get the same bandwidth. They are really for packaging reason more than anything. It could be really useful to put 256 bit and 384 bit GPU into mobile. But It will still be cost prohibitive to do it on larger bus even you reduce by half the amount of chip. At this point HBM start to make sense.

Also they compare it there with HBM2E, but HBM3 is available and have way more bandwidth.

They could do super large bus on professional high end GPU, but it's cheaper and better to do HBM at that point.

Also GDDR7 is around the corner with speed going up to 36 gbps

 

[WhoDecidedThat]

They are really for packaging reason more than anything.

I understand. I thought more about it and your point makes sense..

If you're knowledgeable enough I have a question. AMD is already using advanced packaging technology in RDNA3 right... so why do you think they did not go for a HBM solution?

 

[Punkenjoy]

I understand. I thought more about it and your point makes sense..

If you're knowledgeable enough I have a question. AMD is already using advanced packaging technology in RDNA3 right... so instead of 6 MCDs with 96 MB cache, why not go for a HBM solution?

HBM use an interposer. This is a large piece of silicon and is quite expensive to produce. Think of a large chip under the main CCD + the HBM.

AMD on RDNA3 use an organic substrate like traditional GPU chip (Think like some kind of PCB) and they were able to really shrink the trace on it to allow all the connection. This is way cheaper and this is one of the enabler for chiplets GPU since GPU require way more connection than CPU.

 

[Wirko]

HBM use an interposer. This is a large piece of silicon and is quite expensive to produce. Think of a large chip under the main CCD + the HBM.

AMD on RDNA3 use an organic substrate like traditional GPU chip (Think like some kind of PCB) and they were able to really shrink the trace on it to allow all the connection. This is way cheaper and this is one of the enabler for chiplets GPU since GPU require way more connection than CPU.

RDNA3 is built using something more advanced than a usual substrate: the fan-out RDL. I commented on it here:

AMD Explains the Economics Behind Chiplets for GPUs

AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart...

www.techpowerup.com

I don't know if it's good enough for routing the wires to a HBM stack, though. But AMD also uses some kind of buried silicon bridges (could be very similar to EMIB) for the HMB stacks on their Instinct GPU.

At this point it's very hard to say which applications are better suited for HBM and which are better for GDDR. Both are evolving, but packaging technology is evolving even faster. HBM requires giant memory controllers for multiple 1024-bit wide buses, meaning a lot of silicon. Also, bridges and similar stuff apparently take up a considerable amount of space on the chips that they connect.

 

[Punkenjoy]

RDNA3 is built using something more advanced than a usual substrate: the fan-out RDL. I commented on it here:

AMD Explains the Economics Behind Chiplets for GPUs

AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart...

www.techpowerup.com

I don't know if it's good enough for routing the wires to a HBM stack, though. But AMD also uses some kind of buried silicon bridges (could be very similar to EMIB) for the HMB stacks on their Instinct GPU.

At this point it's very hard to say which applications are better suited for HBM and which are better for GDDR. Both are evolving, but packaging technology is evolving even faster. HBM requires giant memory controllers for multiple 1024-bit wide buses, meaning a lot of silicon. Also, bridges and similar stuff apparently take up a considerable amount of space on the chips that they connect.

you are correct but I tried to keep the explanation simple. it still organic vs being silicon.

I still think HBM require a silicon substrate. we have to remember that those MCD are connect by multiple Infinity fabrics link and those work by serializing the data to have fewer trace.

But one possibility in the future, could be that instead of stacking cache, we stack HBM. This way, the HBM would be on top of silicon and you could still use infinity fabrics and organic substrate to connect to the CGD.

But first, lets see the first chiplets GPU release and see how it perform.