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| Processor | Intel Core 2 Quad Q6600 G0 VID: 1.2125 |
|---|---|
| Motherboard | GIGABYTE GA-P35-DS3P rev.2.0 |
| Cooling | Thermalright Ultra-120 eXtreme + Noctua NF-S12 Fan |
| Memory | 4x1 GB PQI DDR2 PC2-6400 |
| Video Card(s) | Colorful iGame Radeon HD 4890 1 GB GDDR5 |
| Storage | 2x 500 GB Seagate Barracuda 7200.11 32 MB RAID0 |
| Display(s) | BenQ G2400W 24-inch WideScreen LCD |
| Case | Cooler Master COSMOS RC-1000 (sold), Cooler Master HAF-932 (delivered) |
| Audio Device(s) | Creative X-Fi XtremeMusic + Logitech Z-5500 Digital THX |
| Power Supply | Chieftec CFT-1000G-DF 1kW |
| Software | Laptop: Lenovo 3000 N200 C2DT2310/3GB/120GB/GF7300/15.4"/Razer |
Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed memory architectures, today announced the introduction of its memory controller interface solution for industry-standard DDR3 DRAM. The fully integrated hard macro cell provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600MHz.
Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations, and network communications. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) chip.
"As signaling frequencies of mainstream DDR DRAMs continue to increase, the memory interfaces critical to system performance have become very challenging to design," said Martin Scott, senior vice president of engineering at Rambus Inc. "Using our extensive signal integrity experience, we have architected a low-risk, highly optimized DDR3 memory controller interface that meets the performance requirements of both main memory and consumer applications."
To ensure first-silicon success, a reliable system environment for high-volume production, and rapid in-system qualification, the Rambus DDR3 interface solution incorporates Rambus innovations such as:
View at TechPowerUp Main Site
Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations, and network communications. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) chip.
"As signaling frequencies of mainstream DDR DRAMs continue to increase, the memory interfaces critical to system performance have become very challenging to design," said Martin Scott, senior vice president of engineering at Rambus Inc. "Using our extensive signal integrity experience, we have architected a low-risk, highly optimized DDR3 memory controller interface that meets the performance requirements of both main memory and consumer applications."
To ensure first-silicon success, a reliable system environment for high-volume production, and rapid in-system qualification, the Rambus DDR3 interface solution incorporates Rambus innovations such as:
- FlexPhase timing adjustment circuits for precise on-chip data alignment with the clock
- Calibrated output drivers
- On-die termination
- LabStation software environment for bring-up, characterization and validation of the DDR3 interface in the end-user application
- 800 to 1600MHz data rates
- Support for DDR3 and DDR2 signaling modes
- On-chip phase-locked loop (PLL)
- On-chip delay-locked loop (DLL)
- Levelization support for fly-by command and address architecture
- Rambus FlexPhase based in-PHY module that provides characterization and testing capability in the production system
- Multi-drop bus and multi-rank module support for large capacity systems
- Variable data bit-widths (8-, 16-, 32-, and 64-bit) with optional ECC support
View at TechPowerUp Main Site
