Possible AMD Hybrid Phoenix 2 APU Spotted in 2+4 CPU Configuration

[GFreeman]

An alleged AMD Phoenix 2 hybrid APU has been spotted in the MilkyWay@Home database, featuring 2+4 CPU configuration. While the APU was note named, the "A70F80" CPUID apparently is a part of the Phoenix 2 lineup. According to the database entry, the APU in question has two standard Zen 4 and four power-optimized (low-power) Zen 4 cores, making such chip a sort a big.LITTLE-like hybrid configuration. It appears to support multithreading on all six cores.

While the entry does not confirm this is indeed the Phoenix 2 APU, it does matches some previous rumors. Such upcoming APU, as detailed by Tomshardware, is rumored to feature two Zen 4 cores with 2 MB of L2 and 4 MB of L3 cache, and four Zen 4c cores with 4 MB of L2 cache and 4 MB of L3 cache, which is a rather surprising configuration. It should also come with RDNA 3-based iGPU with up to 512 stream processors, and have DDR5/LPDDR5X memory support.



Of course, as this is just an early database entry, you should take it with a rather big grain of salt. The entry suggest that the alleged Phoenix 2 APU has been in the MilkyWay@Home database since early March, indicating that the chip is under testing by someone in AMD or some partner, but we are still far away from the launch as the rumored date for Phoenix 2 APUs is set for the second half of 2023.

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[hs4]

A reporter at the Genoa launch explained that Zen4c for Bergamo is simply a smaller cache version of Zen4. Zen4 has a large caches area (2/3 of CCD is occupied by L2 + L3) but APU already has a reduced cache size. If N4 has a mechanism like FinFlex, it could achieve something that is logically equivalent to Zen4, albeit with a lower maximum clock speed.

 

[LabRat 891]

Seeing AMD making 'efficiency cores' has me wondering about a rebirth of the Geode branding.

 

[Minus Infinity]

A reporter at the Genoa launch explained that Zen4c for Bergamo is simply a smaller cache version of Zen4. Zen4 has a large caches area (2/3 of CCD is occupied by L2 + L3) but APU already has a reduced cache size. If N4 has a mechanism like FinFlex, it could achieve something that is logically equivalent to Zen4, albeit with a lower maximum clock speed.

4C is also only 1T per core IIRC.

MLiD said his inside sources claimed 4c cores would be maybe 20-30% weaker than a full 4 core at most and would be a lot stronger than Intel's Gracemont e-cores.
I would love to see a Phoenix 8+8 hybrid apu with RDNA3 iGPU. This would take it right to the 13700K and be more desirable than either 7800X or 7900X to me.

 

[Mawkzin]

4C is also only 1T per core IIRC.

MLiD said his inside sources claimed 4c cores would be maybe 20-30% weaker than a full 4 core at most and would be a lot stronger than Intel's Gracemont e-cores.
I would love to see a Phoenix 8+8 hybrid apu with RDNA3 iGPU. This would take it right to the 13700K and be more desirable than either 7800X or 7900X to me.

4c is SMT.

 

[hs4]

4C is also only 1T per core IIRC.

MLiD said his inside sources claimed 4c cores would be maybe 20-30% weaker than a full 4 core at most and would be a lot stronger than Intel's Gracemont e-cores.
I would love to see a Phoenix 8+8 hybrid apu with RDNA3 iGPU. This would take it right to the 13700K and be more desirable than either 7800X or 7900X to me.

At the ADL stage, the E core has 0.3x area and 0.5x MT performancerelative to the P core, with an area efficiency of 1.6x MT performance. Based on the announced number of Bergamo's cores, we can estimate that Zen4c is still aiming for 1.6x area efficiency with 0.5x area at 0.8x performance.

For AMD, Bergamo is a priority, and as Intel is also developing Sierra Forrest, I believe that competing with ARM Neoverse is the central motivation.

This 2C+4c is considered almost equivalent to 2+8 after MTL in Intel and will be used for almost the same purpose (to complement the entry segment and for ultra mobile). It will replace Mendocino in the future.