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In the latest Linux Kernel patches, Intel engineers are submitting initial support for Meteor Lake processor generation, with some interesting potential features. In a patch submitted yesterday, the Intel engineer noted, "On MTL, GT can no longer allocate on LLC - only the CPU can. This, along with the addition of support for ADM/L4 cache, calls a MOCS/PAT table update." What this translates to is that starting from Meteor Lake, the integrated graphics can no longer allocate on the last-level cache (LLC), the highest numbered cache accessed by the cores before fetching from memory. Instead, only the CPU cores can allocate to it. Even more interesting is the mention of the Meteor Lake platform's level 4 (L4) cache. For the first time since Haswell and Broadwell, Intel may be planning to bring back the L4 cache and integrate it into the CPU.
Usually, modern processors use L1, L2, and L3 caches where the L1 version is the fastest and smallest, while the others are larger but slower. The inclusion of L4 caches often is unnecessary, as this type of cache can consume a big area on the processor die while bringing little benefit, translating to the cost of manufacturing drastically soaring. However, with Meteor Lake and its multi-die tile design, we wonder where the L4 cache will end up. We could see integration into the base tile, which holds the compute cores and essential compute elements. This makes the most sense since the logic needs access to fast memory, and L4 could improve the performance in specific applications.
View at TechPowerUp Main Site | Source
Usually, modern processors use L1, L2, and L3 caches where the L1 version is the fastest and smallest, while the others are larger but slower. The inclusion of L4 caches often is unnecessary, as this type of cache can consume a big area on the processor die while bringing little benefit, translating to the cost of manufacturing drastically soaring. However, with Meteor Lake and its multi-die tile design, we wonder where the L4 cache will end up. We could see integration into the base tile, which holds the compute cores and essential compute elements. This makes the most sense since the logic needs access to fast memory, and L4 could improve the performance in specific applications.
![](https://www.techpowerup.com/img/aEwte3sA4GfxAdCZ_thm.jpg)
![](https://www.techpowerup.com/img/UXrILB5TTK0ldqUW_thm.jpg)
View at TechPowerUp Main Site | Source