AMD Ryzen 8000 "Granite Ridge" Zen 5 Processor to Max Out at 16 Cores

[btarunr]

AMD's next-generation Ryzen 8000 "Granite Ridge" desktop processor based on the "Zen 5" microarchitecture, will continue to top out at 16-core/32-thread as the maximum CPU core-count possible, says a report by PC Games Hardware. The processor will retain the chiplet design of the current Ryzen 7000 "Raphael" processor, with two 8-core "Zen 5" CCDs, and one I/O die. It's very likely that AMD will reuse the same 6 nm client I/O die (cIOD) as "Raphael," just the way it used the same 12 nm cIOD between Ryzen 3000 "Matisse" and Ryzen 5000 "Vermeer;" but with updates that could enable higher DDR5 memory speeds. Each of the up to two "Eldora" Zen 5 CCDs has 8 CPU cores, with 1 MB of dedicated L2 cache per core, and 32 MB of shared L3 cache. The CCDs are very likely to be built on the TSMC 3 nm EUV silicon fabrication process.

Perhaps the most interesting aspect of the PCGH leak would have to be the TDP numbers being mentioned, which continue to show higher-performance SKUs with 170 W TDP, and lower tiers with 65 W TDP. With its CPU core-counts not seeing increases, AMD would bank on not just the generational IPC increase of its "Zen 5" cores, but also max out performance within the power envelope of the new node, by dialing up clock speeds. AMD could ride out 2023 with its Ryzen 7000 "Zen 4" processors on the desktop platform, with "Granite Ridge" slated to enter production only by Q1-2024. The company could update its product stack in the meantime, perhaps even bring the 4 nm "Phoenix" monolithic APU silicon to the Socket AM5 desktop platform. Ryzen 8000 is expected to retain full compatibility with existing Socket AM5, and AMD 600-series chipset motherboards.



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[Xuper]

AM5 is dead? AM6?

 

[3x0]

AM5 is dead? AM6?

No

Ryzen 8000 is expected to retain full compatibility with existing Socket AM5, and AMD 600-series chipset motherboards.

 

[csendesmark]

Hope AMD will keep adding extra PCIe lanes just like with the Ryzen 7000 family!

 

[TumbleGeorge]

What is written is still hearsay. Strangely, there is no mention of XDNA(AI) in this material. ZEN 5 without artificial intelligence? Hardly!

 

[Daven]

I hope to see three things happen with Zen 5:

1- Huge IPC increase
2- Major improvements to IMC
3- Hardening for higher clocks

That last one should be tailored to remove any shenanigans with X3D BIOS tinkering.

 

[Chaitanya]

Hopefully the memory controller will be updated.

 

[AnarchoPrimitiv]

I hope to see three things happen with Zen 5:

1- Huge IPC increase
2- Major improvements to IMC
3- Hardening for higher clocks

That last one should be tailored to remove any shenanigans with X3D BIOS tinkering.

Leaks have already said Zen5 should have a large IPC increase, it's pretty much a brand new architecture they've claimed.

What I want to know is whether AMD will do something like this: combine a "regular" Zen5 Chiplet with a Zen5C chiplet (so the same two chiplet setup), but then you'd have 8 full power Zen5 cores from the first chiplet and then 16 Zen5c cores from the second chiplet (perhaps the reduced cache on the Zen5C chiplet could be offset by a v-cache addition?) and then you'd have a 24 core 48 thread hybrid Zen5 chip for AM5.

 

[Vya Domus]

What is written is still hearsay. Strangely, there is no mention of XDNA(AI) in this material. ZEN 5 without artificial intelligence? Hardly!

Doesn't it clearly says "Integrated AI and machine learning optimizations" ?

Regardless, these ML accelerators aren't really supported by anything as far as I can tell, for the time being they are useless.

 

[TumbleGeorge]

Doesn't it clearly says "Integrated AI and machine learning optimizations" ?

Regardless, these ML accelerators aren't really supported by anything as far as I can tell, for the time being they are useless.

On slide yes, in article text no.
PS. In Windows 11 has integrated AI features from few months.

 

[MikeGR7]

The Hype machine started already?

I wonder if there are still people falling for AMDs failed chiplet architecture.
I mean okay i get it that media pushes them hard but after lagfest to lagfest cpu release you would think that people would see through the lies.

Ryzen 5 first predictions: 1 minute pauses during gameplay so the huge L3 caches start to fill
Ground Breaking DDR5 7000 support when DDR5 12000 becomes mainstream
PCIE GEN 5 support and reverse company stance (again) saying that competitions GEN 6 is useless
"Slower by design because eco"
Outrageous prices because "people will support the alternative"
30 minutes boot time

 

[bug]

I'm sure that means some technical limitation at work, but let's be honest, 16c/32t will probably still be overkill for a desktop 10 years from now.

 

[Guwapo77]

I don't even remotely care about the core count, just show me improvements in performance and stability.

 

[Tomorrow]

Retaining 16c with 8c CCD's is what other leaks have said but the 3nm by Q1 2024 rumor is BS. Zen5 will not utilize 3nm for desktop mainstream or even mainline server chips. The only Zen5 product to use this will be Zen5c (dense, with more cores and less cache. Think: Bergamo) that will come out later when 3nm is at capacity. Certainly not at Q1 2024.

Zen5 in general will utilize mature 4nm while bringing big architectural changes. So i dont expect changes in core counts or clock speeds. Or even L3 cache amounts.

 

[Metroid]

16 cores 32 threads is very much enough for games at this time and age, even 8 cores is enough now and looking forward next 3 years or so. I rather have a better single core performance than having more cores.

 

[Daven]

Retaining 16c with 8c CCD's is what other leaks have said but the 3nm by Q1 2024 rumor is BS. Zen5 will not utilize 3nm for desktop mainstream or even mainline server chips. The only Zen5 product to use this will be Zen5c (dense, with more cores and less cache. Think: Bergamo) that will come out later when 3nm is at capacity. Certainly not at Q1 2024.

Zen5 in general will utilize mature 4nm while bringing big architectural changes. So i dont expect changes in core counts or clock speeds. Or even L3 cache amounts.

You are probably right.

Apple Books Nearly 90% of TSMC's 3nm Production Capacity for This Year

Apple has booked nearly 90% of chip supplier TSMC's first-generation 3-nanometer process capacity this year for future iPhones, Macs, and iPads,...

www.macrumors.com

 

[AusWolf]

Ryzen 5 first predictions: 1 minute pauses during gameplay so the huge L3 caches start to fill

The article says cache size is expected to be 32 MB, which is exactly the same as Zen 3 and Zen 4.

Ground Breaking DDR5 7000 support when DDR5 12000 becomes mainstream

In 2024? Yeah, right...

PCIE GEN 5 support and reverse company stance (again) saying that competitions GEN 6 is useless

AMD has been pioneering new PCI-e standards, even though they are useless at first.

"Slower by design because eco"

What does that even refer to?

Outrageous prices because "people will support the alternative"

Show me some outrageous prices from AMD. Apart from X670(E) motherboards, I don't see any.

30 minutes boot time

Have you heard about "Memory Context Restore"?

 

[gasolina]

Ryzen 7000 delid reduce the temp around 2x*c and amd being an bad boy for making cpu consume power so little yet so damn hot.....

 

[unwind-protect]

I for one am disappointed. Was hoping for 24 cores.

 

[A Computer Guy]

AMD has been pioneering new PCI-e standards, even though they are useless at first.

I imagine they have been using these technologies in the server space first where there is larger interest in increasing bandwidth epically with virtualization.

 

[Wolverine2349]

The worst part of all of that is the fact that it will still be 2 8 core CCDs which means severe cross latency penalty for more than 8 cores.

Why not find a way to top out at 16 cores but have them on one CCD.

Still stuck at only 8 cores on one CCD.

Not good at all.

 

[A Computer Guy]

The worst part of all of that is the fact that it will still be 2 8 core CCDs which means severe cross latency penalty for more than 8 cores.

Why not find a way to top out at 16 cores but have them on one CCD.

Still stuck at only 8 cores on one CCD.

Not good at all.

Make one CCD of e-cores and one CCD of p-cores. This is the way!

 

[Wolverine2349]

Make one CCD of e-cores and one CCD of p-cores. This is the way!

No make a CCD with 16 cores one with 12 and one with 8.

E-cores the heck with them.

 

[TumbleGeorge]

I don't know why some still keep pushing BS for ZEN 5 in Q1 2024? We'll be lucky as AMD is on schedule to release the first 1-2 models that will lead the consumer class in November or even as late, in December 2024. A real massive presence of CPUs with ZEN 5 architecture I don't expect until after 12 -14 months. So, at the end of 2024, a very small fraction of TSMC's 3Nx capacity will probably be enough for them.

 

[Tomorrow]

The worst part of all of that is the fact that it will still be 2 8 core CCDs which means severe cross latency penalty for more than 8 cores.

Why not find a way to top out at 16 cores but have them on one CCD.

Still stuck at only 8 cores on one CCD.

Not good at all.

That would be (by definition) monolithic. With 16c CCD they could have 32c/64t Ryzen 9 models but i doubt that happens before Zen6.
And using only one chiplet say in 8600X would mean that a lot would go to waste. 10 out of 16 cores would need to be defective or fused off.

At the high end say 8950X it would be cheaper with one 16c chiplet but at the lower end it would make things more expensive.