TPU Interviews AMD Vice President: Ryzen AI, X3D, Zen 4 Future Strategy and More

[NC37]

Good to see AMD isn't going to mess with that E cores garbage. It has been a problem on lots of software and games and it has been a problem going back to the 90s in consoles. Jaguar and Saturn both had processors running at different speeds and it became a well known issue with devs trying to get them to work together and balance out. Ultimately, it is more of a headache than not. Intel gimping hardware for benchmarks.

 

[TechLurker]

Kind of wish there was a question and answer about expanding on PCIe lanes at the top end; to bridge more of the gap between high-end Ryzen and low-end Threadripper Pro, since there are no longer any regular TRs. Which would be ideal in parallel with having quad memory.

 

[W1zzard]

Kind of wish there was a question and answer about expanding on PCIe lanes at the top end; to bridge more of the gap between high-end Ryzen and low-end Threadripper Pro, since there are no longer any regular TRs. Which would be ideal in parallel with having quad memory.

Interesting question, I only had 1 hour face time, which is still a lot for a VP. Also seems a bit on the to technical side.

I feel like the trend is actually to have fewer lanes, because lanes = die space = money. Everybody is hoping that Gen 5 proliferation will let people build SSDs with x2, mobile GPUs with x4, chipset link with x2, because "good enough"

 

[atomsymbol]

Marketing speeches related to the forthcoming Zen 5 CPU architecture are pointless without at least providing a block diagram of the "re-pipelined front-end and wider issue".

 

[TechLurker]

Interesting question, I only had 1 hour face time, which is still a lot for a VP. Also seems a bit on the to technical side.

I feel like the trend is actually to have fewer lanes, because lanes = die space = money. Everybody is hoping that Gen 5 proliferation will let people build SSDs with x2, mobile GPUs with x4, chipset link with x2, because "good enough"

Eh, if anything, with how many want more options; there should be more lanes. I get that for thin clients, Nuc-likes and SFF builds, having a stronger APU with a few lanes just for the things you've listed would be "good enough", but there's a distinct gap for those who populate their boards as mini-servers, or storage, or even dual-use PCs. The HEDT crowd who needs more PCI lanes are kind of left out cold, as Threadripper was the last real HEDT consumer level CPU to offer plenty of lanes for a bit more cost, and that's since been moved solely to the Professional side for a considerable markup.

Given how advanced Ryzen has been getting in both core counts and performance, there's no reason to not have higher end boards+CPUs with 36-48 lanes allowing full use of 2 x16 slots and some peripherals, as it used to be years ago with plenty of PCIe 2.0 boards with Triple Channel Memory and up to 8 x16 lanes for then ridiculous Dual/Triple/Quad GPU builds. Heck, if PCIe 5.0 is the goal, they could at least break out the usual 24 PCIe lanes into 48 by downgrading the slots to cheaper 4.0, offering up at least 2 x16 lanes that can basically run any GPU or large NVME storage for the next couple of years, and still run plenty fast enough PCIe 4.0 peripherals off the remaining slots and STILL populate the SATA ports if so desired.

 

[ikjadoon]

They seem to like x86s… hopefully the result is more performant and power efficient chips. Perhaps denser designs, more cores.

X86S is only a boot / UEFI optimization. It will have no impact on perf / power / area / design etc.

Presumably, Intel is laying the groundwork for 64-bit-only execution, but that's decades away and it will not be X86S.

 

[Nanochip]

X86S is only a boot / UEFI optimization. It will have no impact on perf / power / area / design etc.

Presumably, Intel is laying the groundwork for 64-bit-only execution, but that's decades away and it will not be X86S.

How can you say there will be no impact? if silicon is no longer dedicated to execute old obsolete instructions, could that not lead to them using the net savings in silicon die area for other things ?

 

[ikjadoon]

How can you say there will be no impact? if silicon is no longer dedicated to execute old obsolete instructions, could that not lead to them using the net savings in silicon die area for other things ?

Fair: instead of no impact, I should write imperceptible, unmeasurable, virtually none, invisible, etc. It's overdue housekeeping that might one day lay the groundwork for something bigger.

Intel has exhaustively defined X86S. In terms of perf / power / area / design, X86S is adjusting the tiniest, smallest, lowest-power segments of a CPU's architecture (not the CPU nor microarchitecture). For example, most agree there's nothing special in the Arm ISA that makes it inherently more efficient than X86: the same conclusion should also apply to X86S.

Intel states X86S reduces complexity versus X86: the CPUs are easier / faster to bring up, validate, test, etc. Emphasis mine:

A 64-bit mode-only architecture removes some older appendages of the architecture, reducing the overall complexity of the software and hardware architecture.

From an SoC engineer at Intel,

The benefit is mostly that it cleans out the unused parts of a die. The real estate used is relatively small compared to the large-scale features like CPU cores, but it's still an almost completely unused part of the design.

The real heavy hitters are the loss of 16-bit address support, as this will make memory controller design possibly simpler, and the removal of multiple internal rings. These things just sit there, consuming some non-zero power whenever the chip is on, and are completely unused by a modern OS. The new handling of internal interrupts should help future IPC improvements if it's tied into other parts of the CPU correctly.

The power draw is tiny, and I mean tiny, but never exactly 0.

Simplification is the big win here.

It might have user-noticeable benefits after a few clean-sheet designs + new OSes, but it's going to take many, many years.

 

[Nanochip]

Fair: instead of no impact, I should write imperceptible, unmeasurable, virtually none, invisible, etc. It's overdue housekeeping that might one day lay the groundwork for something bigger.

Intel has exhaustively defined X86S. In terms of perf / power / area / design, X86S is adjusting the tiniest, smallest, lowest-power segments of a CPU's architecture (not the CPU nor microarchitecture). For example, most agree there's nothing special in the Arm ISA that makes it inherently more efficient than X86: the same conclusion should also apply to X86S.

Intel states X86S reduces complexity versus X86: the CPUs are easier / faster to bring up, validate, test, etc. Emphasis mine:



From an SoC engineer at Intel,



It might have user-noticeable benefits after a few clean-sheet designs + new OSes, but it's going to take many, many years.

Cool beans. Thanks for taking the time to indulge me and provide additional context. I really do appreciate. I was wondering what the net savings were for intel.