Ryzen Owners Zen Garden

[Space Lynx]

Vcache might still be on an old node, if that's what you were getting at. Totally slipped my mind that 7000X3D no longer stacks like-on-like and continues to use N7 for Vcache. If cache not shrinking created a big enough challenge to disaggregate RDNA into chiplets, dunno how much longer this 7nm Vcache is going to last. There was a die shot somewhere that already showed the cache die not fitting neatly into the N5 CCD anymore and the design changes they had to make to get around that.

nice plot twist, this is why I ask strange questions

at end of day it doesn't matter, I just think it is interesting. would be neat if AMD swings a homerun and launches 4nm 8800x3d and just smashes Intel to bits and bobs. Phoenix is on 4nm, so maybe they got a little trick up their sleeve to surprise us all. I wouldn't expect more than 10% gains if they stay on same node, but a jump to 4nm, maybe 30%... and Jim Keller did state that the 8800x3d jump from 7800x3d would be around 30% from what I remember reading in an interview he did recently...

30% gains would be epic.

edit: can't find the article now, so i guess I am pulling that 30% from nowhere, maybe I dreamed it. wouldn't be the first time my dreams were in PC parts, lmao

 

[AusWolf]

7000X3D no longer stacks like-on-like and continues to use N7 for Vcache.

Seriously? How did they manage to stack it, then? A 64 MB cache chip on N7 should be bigger than the N5 CCD.

 

[TheLostSwede]

Interesting chart, thanks. They may have problems, but they won't disappoint their trillion dollar overlord Apple, 3nm will be in mass supply next year I am certain. So 9900x3d will be the 3nm node is logical.

You have to learn to separate the various nodes. If you look at the chart above, technically the NxP ones are for PC CPUs, whereas Arm based chips can be a year or two earlier on a different node with the same number. As such, you can't make assumptions like that, as not all nodes are suitable for PC CPUs.

 

[AusWolf]

would be neat if AMD swings a homerun and launches 4nm 8800x3d and just smashes Intel to bits and bobs.

You don't have to wait for that. Zen 4 X3D already smashes Intel 13th gen to pieces in both gaming performance and efficiency.

 

[TheLostSwede]

Vcache might still be on an old node, if that's what you were getting at. Totally slipped my mind that 7000X3D no longer stacks like-on-like and continues to use N7 for Vcache. If cache not shrinking created a big enough challenge to disaggregate RDNA into chiplets, dunno how much longer this 7nm Vcache is going to last. There was a die shot somewhere that already showed the cache die not fitting neatly into the N5 CCD anymore and the design changes they had to make to get around that.

It's better all-around for efficiency and consistency if they stick to optimizing a similar node as last gen, keeping the same clock envelope and going after bigger cores instead.

The Vcache will most likely not shrink for some time, but rather be perfected on the current node, especially in terms of being able to handle higher thermals and being more affordable to produce. This is just my guess though, but considering that some parts of a CPU don't shrink as well as others, which is also in part what led to AMD's chiplet approach, I have a feeling the Vcache will be another part where AMD will try to make improvements on an already tried and tested node, rather than trying to move to a new node as quickly as their bank accounts allow them to. That said, we might see a shift to N6, which just like N4 is a node optimisation rather than a real die shrink.

 

[tabascosauz]

nice plot twist, this is why I ask strange questions

at end of day it doesn't matter, I just think it is interesting. would be neat if AMD swings a homerun and launches 4nm 8800x3d and just smashes Intel to bits and bobs. Phoenix is on 4nm, so maybe they got a little trick up their sleeve to surprise us all. I wouldn't expect more than 10% gains if they stay on same node, but a jump to 4nm, maybe 30%... and Jim Keller did state that the 8800x3d jump from 7800x3d would be around 30% from what I remember reading in an interview he did recently...

30% gains would be epic.

edit: can't find the article now, so i guess I am pulling that 30% from nowhere, maybe I dreamed it. wouldn't be the first time my dreams were in PC parts, lmao

Node fixation is so 2019

If new CCD is destined for N4, AMD better have made big strides in securing supply. Phoenix "launch" was a complete disaster and does anything but instill confidence in N4. Won't be smashing anything except their own product line unless situation improves, which it probably will.

Highlight of Phoenix is Zen 4, not N4. Big clockspeed bump for 780M amounted to very little over 680M, Zen 4 actually seems to drive some of the actual tangible differences (better frametime consistency and user experience in otherwise similar perf).

Seriously? How did they manage to stack it, then? A 64 MB cache chip on N7 should be bigger than the N5 CCD.

An article implied they did some reshuffling because the new cache die is not the same design or size as the old one despite both being N7. Maybe similar manner to Zen 4c. It's still not bigger than the CCD but is starting to intrude on other stuff.

The N3 overview that swede linked spells out the same bad news for cache scaling on N3, so maybe a new solution is imminent.

 

[Space Lynx]

You don't have to wait for that. Zen 4 X3D already smashes Intel 13th gen to pieces in both gaming performance and efficiency.

oh this isn't about performance for me, i already know 8800x3d will become king, its more just about the curiosity of these things. sometimes I wonder if companies like TSMC overestimate their capabilities because they have to fulfill the will of their trillion dollar masters, what if we get to like sub 2nm node and the plan to keep shrinking just utterly collapses and the industry uses 3nm node for the next 20 years. i want to write a sci-fi novella about that, lmao

 

[Launcestonian]

As an experiment, I booted up my Corsair CMH32GX5M2B5600C36 in its XMP profile with Agesa 1.0.0.7c on my Gigabyte board, CPU with PBO enabled, & the FCLK was at 2000! This is not in accordance with the theories floating around the web about the mathematics of relationship between FCLK & MEMCLK ratio of 1:3 in Zen 4. So what's the deal here?

 

[AusWolf]

An article implied they did some reshuffling because the new cache die is not the same design or size as the old one despite both being N7. Maybe similar manner to Zen 4c. It's still not bigger than the CCD but is starting to intrude on other stuff.

The N3 overview that swede linked spells out the same bad news for cache scaling on N3, so maybe a new solution is imminent.

Have you got the link for that article? It would be interesting to read about this. Considering that the cache runs at the same frequency as the CPU cores, and that shrinking the cores will eventually make the cache die not fit on top, I'm wondering how AMD will continue making improvements on future X3D chips.

 

[tabascosauz]

the industry uses 3nm node for the next 20 years. i want to write a sci-fi novella about that, lmao

They'll just come up with a new name for an "optimization" every year. After all, the alphabet gives you more options than just adding extra + signs

No but seriously, I don't see AMD needing to push the freq range significantly. Ball is in Intel's court and hiking up clocks on 14th gen should be pretty easy to match with just a new core alone. They can sit pretty for a while, so N4 makes a lot of sense.

Last time they did that it was a recipe for success (Ryzen 5000). More efficient, durable, reliable = happy customers

As an experiment, I booted up my Corsair CMH32GX5M2B5600C36 in its XMP profile with Agesa 1.0.0.7c on my Gigabyte board, CPU with PBO enabled, & the FCLK was at 2000! This is not in accordance with the theories floating around the web about the mathematics of relationship between FCLK & MEMCLK ratio of 1:3 in Zen 4. So what's the deal here?

First I've ever heard of this "theory". No one is running FCLK at 1000 just to get a supposedly magical 1:3 relationship with MCLK or UCLK. It's decoupled this gen for a reason.

@AusWolf I don't remember, but whichever article talks about Raphael Vcache being 7nm and the die shot of Raphael next to Raphael-X.

 

[AusWolf]

As an experiment, I booted up my Corsair CMH32GX5M2B5600C36 in its XMP profile with Agesa 1.0.0.7c on my Gigabyte board, CPU with PBO enabled, & the FCLK was at 2000! This is not in accordance with the theories floating around the web about the mathematics of relationship between FCLK & MEMCLK ratio of 1:3 in Zen 4. So what's the deal here?

FCLK (the infinity fabric) isn't paired with your memory clock. UCLK (the memory controller) is.

oh this isn't about performance for me, i already know 8800x3d will become king

Probably... unless Intel comes up with some serious improvements. We can never now. That's why I think speculating about future products is pointless. If something grabs your fancy now, go for it.

@AusWolf I don't remember, but whichever article talks about Raphael Vcache being 7nm and the die shot of Raphael next to Raphael-X.

Googling for "raphael-x die shot" gives me some gory fan fiction images of the teenage mutant ninja turtles, but I'll keep looking.

 

[TheLostSwede]

As an experiment, I booted up my Corsair CMH32GX5M2B5600C36 in its XMP profile with Agesa 1.0.0.7c on my Gigabyte board, CPU with PBO enabled, & the FCLK was at 2000! This is not in accordance with the theories floating around the web about the mathematics of relationship between FCLK & MEMCLK ratio of 1:3 in Zen 4. So what's the deal here?

When was it ever 1:3?

 

[Mussels]

I wouldn't count on anyone "knowing" anything before an official announcement is made.

As someone in-the-loop on these things, theres nothing to go by yet.

Usually refined chips (2nd/3rd gen) of a node are the best ones anyway, unless some dumb decisions are made - like intels 2nd and 3rd gen series, 3rd gen was superior in every way except they stopped soldering the IHS

FCLK (the infinity fabric) isn't paired with your memory clock. UCLK (the memory controller) is.

I'm quite sure i'll trip myself up on this one a few times, too. It's brain-hurty going from AM4 to AM5 where they behave differently

 

[AusWolf]

I'm quite sure i'll trip myself up on this one a few times, too. It's brain-hurty going from AM4 to AM5 where they behave differently

It's pretty easy, though. FCLK = 2000 MHz, and UCLK = MCLK or MCLK/2.

 

[Mussels]

It's pretty easy, though. FCLK = 2000 MHz, and UCLK = MCLK or MCLK/2.

Yeah but on AM4 we had "ram and not ram"


I can't wait til i can satisfy my OCD with all the variations on that. Driving me nuts not knowing for sure if 2000 is the final answer for all memory speeds or just 6000MT/s, or if mathing out combinations is better.

 

[Launcestonian]

When was it ever 1:3?

View attachment 311836

2000FCLK is mean't to be for 6000MT/S memory, that was my point, according to the theories floating around the net, but as you can see it's not.

 

[TheLostSwede]

2000FCLK is mean't to be for 6000MT/S memory, that was my point, according to the theories floating around the net, but as you can see it's not.
View attachment 311982

No...
I have 6000 MHz RAM, you have 5600 MHz RAM, so the MCLK and UCLK will be different, but the FCLK is the same, since it's not related to the other two any more.

 

[tabascosauz]

2000FCLK is mean't to be for 6000MT/S memory, that was my point, according to the theories floating around the net, but as you can see it's not.

Is there something we're all missing here......? Literally never have I seen any of these "theories on the net". There is no necessary correlation between Fabric and UCLK on this generation, period, there's not "meant to be". It's not AM4 anymore.

You also haven't explained your 1:3 idea: at your current settings, theoretical 1:3 would require something like 933 FCLK (appalling performance) or 6000 UCLK (DDR5-12000 is not currently possible). DDR5-6000 is not 6000 UCLK - UMC clock is 3000MHz.

2000FCLK is the accepted starting point for good performance, going higher than 2000 is better but only if stable and without performance regressions. UCLK should be 1:1 with MCLK for best performance, until around or just shy of DDR5-8000 (4000 MCLK and 2000 UCLK) when 1:2 UCLK begins to become worthwhile.

 

[trparky]

2000FCLK is the accepted starting point for good performance, going higher than 2000 is better but only if stable and without performance regressions.

I run mine at 2030 MHz as per a Buildzoid video.

 

[Launcestonian]

No...
I have 6000 MHz RAM, you have 5600 MHz RAM, so the MCLK and UCLK will be different, but the FCLK is the same, since it's not related to the other two any more.

For 1:3 to work it would need 1866 speed but it's not available. Probably due to the valid combinations of multipliers and dividers that are available for the IF clock. There are many speeds missing that you'd expect to be there... No 1700, 1900, 2300.

It is most likely that AMD believes that the increased latency penalty of the FIFO not having a nice ratio like 1:2 or 1:3 doesn't really matter it seems. They improved their FIFO (queue) design for crossing clock domains since Zen3. But, as an overclocker, I care about tiny details like this, unlike 99.99% of their customers.

Is there something we're all missing here......? Literally never have I seen any of these "theories on the net". There is no necessary correlation between Fabric and UCLK on this generation, period, there's not "meant to be". It's not AM4 anymore.

You also haven't explained your 1:3 idea: at your current settings, theoretical 1:3 would require something like 933 FCLK (appalling performance) or 6000 UCLK (DDR5-12000 is not currently possible). DDR5-6000 is not 6000 UCLK - UMC clock is 3000MHz.

2000FCLK is the accepted starting point for good performance, going higher than 2000 is better but only if stable and without performance regressions. UCLK should be 1:1 with MCLK for best performance, until around or just shy of DDR5-8000 (4000 MCLK and 2000 UCLK) when 1:2 UCLK begins to become worthwhile.

AMD training team has pretty much confirmed there will be latency benefits for 1:3 ratios, its due to the Fifo buffer synchronization, of course the best would be 1:1 sync, but FCLK cant run that high, so the next best thing is 1:3 eg. 3 x 2133=6400 etc. If you want to run that out of sync, it can generally overcome that with much higher mhz. So yes 6000:2200 will be better then 6000:2000, even if not strictly1:3, since that 200mhz bonus and the higher bandwidth will be worth it. Same as 6100:2167/2200 is worthy. But 6400:2133 proves to be tiny better then 6400:2167. There's only a small 33mhz difference, and less gains. If you want to read more about it check out sampsonjackson posts on reddit.

 

[tabascosauz]

For 1:3 to work it would need 1866 speed but it's not available. Probably due to the valid combinations of multipliers and dividers that are available for the IF clock. There are many speeds missing that you'd expect to be there... No 1700, 1900, 2300.

It is most likely that AMD believes that the increased latency penalty of the FIFO not having a nice ratio like 1:2 or 1:3 doesn't really matter it seems. They improved their FIFO (queue) design for crossing clock domains since Zen3. But, as an overclocker, I care about tiny details like this, unlike 99.99% of their customers.


AMD training team has pretty much confirmed there will be latency benefits for 1:3 ratios, its due to the Fifo buffer synchronization, of course the best would be 1:1 sync, but FCLK cant run that high, so the next best thing is 1:3 eg. 3 x 2133=6400 etc. If you want to run that out of sync, it can generally overcome that with much higher mhz. So yes 6000:2200 will be better then 6000:2000, even if not strictly1:3, since that 200mhz bonus and the higher bandwidth will be worth it. Same as 6100:2167/2200 is worthy. But 6400:2133 proves to be tiny better then 6400:2167. There's only a small 33mhz difference, and less gains. If you want to read more about it check out sampsonjackson posts on reddit.

Yes, I am aware of u/sampsonjackson being AMD staff, but not even anything he says contradicts any of the usual suggestions. those same comments literally just reaffirm to run Fabric as fast as possible and stable as possible starting at 2000. Early testing and slides confirmed that 2000 is the place to start, dropping lower FCLK just to achieve some sort of ratio is pure copium.

AM4 had similar phenomena, certain Fabric speeds were still more optimal than others when all running unsynced UCLK, but in the end it amounted to 0 usefulness even for OC.

In any case, as a self-described overclocker, getting to and testing 8000 with A-die is probably where you should be at instead of overthinking 5600, since there is actually a 1:1 ratio at that point and might be worth testing this idea.

 

[Launcestonian]

Yes, I am aware of u/sampsonjackson being AMD staff, but not even anything he says contradicts any of the usual suggestions. those same comments literally just reaffirm to run Fabric as fast as possible and stable as possible starting at 2000. Early testing and slides confirmed that 2000 is the place to start, dropping lower FCLK just to achieve some sort of ratio is pure copium.

AM4 had similar phenomena, certain Fabric speeds were still more optimal than others when all running unsynced UCLK, but in the end it amounted to 0 usefulness even for OC.

In any case, as a self-described overclocker, getting to and testing 8000 with A-die is probably where you should be at instead of overthinking 5600, since there is actually a 1:1 ratio at that point and might be worth testing this idea.

View attachment 312066

I am not overthinking 5600MT/S, it was surprising to see it booting with 2000FCLK if everything else is left on auto & only XMP profile enabled. As a fun experiment I also booted with 5800MT/S & the FCLK dropped to 1933, then of course when booting at 6000MT/S with the same XMP timings from the default XMP profile, the FCLK is now at 2000 again. Seems to me there is some kind of compatibility thing going on here cause' most consumers of XMP profiled ram will just "lock n' load" so to speak & not worry about FCLK speed & thus overall efficiency of their systems. The tricky thing with running FCLK at the highest speed one can is that because of the peculiarities of Zen 4, if its unstable then error correction will occur & this is not a good thing - its also difficult to pick up with stress testing & benching.

 

[AusWolf]

Guys, just stop overthinking the Zen 4 IF. It runs at 2000 MHz. That's it.

 

[Launcestonian]

Guys, just stop overthinking the Zen 4 IF. It runs at 2000 MHz. That's it.

Yeah, I get it. Overthinking has nothing to do with this, if that was the case then about 90% of comments on computer enthusiasts forums would be classed as that.
If AMD claim the 'sweet spot' for Zen 4 is 6000MT/S & yet if the end user does not touch the FCLK setting & leave it on auto, it boots with 2000 FCLK so, there's your 1:3 ratio right there.
I pointed out even booting with 5600MT/S & FCLK setting on auto, its still boots with 2000 FCLK as I indicated further back in this thread & was wondering why this is, yet a net search reveals many conflicting theories about this phenomena.
Latency can be reduced with higher FCLK setting, but how high depends on the silicon lottery luck with any given SKU.

 

[TheLostSwede]

Yeah, I get it. Overthinking has nothing to do with this, if that was the case then about 90% of comments on computer enthusiasts forums would be classed as that.
If AMD claim the 'sweet spot' for Zen 4 is 6000MT/S & yet if the end user does not touch the FCLK setting & leave it on auto, it boots with 2000 FCLK so, there's your 1:3 ratio right there.
I pointed out even booting with 5600MT/S & FCLK setting on auto, its still boots with 2000 FCLK as I indicated further back in this thread & was wondering why this is, yet a net search reveals many conflicting theories about this phenomena.
Latency can be reduced with higher FCLK setting, but how high depends on the silicon lottery luck with any given SKU.

No it's NOT!
FFS, read what people are replying to you. There have NEVER been a 1:3 ratio as the FCLK is decoupled from the other two.