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- Mar 21, 2016
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It seems like a lot of people are kind of hopping on the Intel hate train w/o really any of us being briefed fully on how APO operates and why it can or isn't being supported for 12th gen and 13th gen. I suspect their gate keeping pretty hard highhandedly against 13th gen while 12th wouldn't provide the same tangible uplift we see with 14th gen for APO that could probably be nearly identical for 13th gen as well.
I saw that based upon how I suspect APO operates based on post I had made on TPU around E cores shared cache and intelligently utilizing it to reduce latency, but also has a side benefit of dropping power consumption and temperatures as well that translates to power savings and/or higher performance in tandem with boosting algorithms. It could provide higher peak performance for a individual cooling restraints or longer boost duration for higher sustained performance. In either case it's a net positive.
Basically suspect Intel has mimicked disabling of CCX cores on AMD side to provide uplift within the E core cluster. It's a bit like treating each core within a cluster of E cores as a CCX if it operates as I suspect it does and then cleverly dynamically enabling or disabling them based upon the workload. It's not going to to provide performance uplift for the same reasons, but in lighter workloads that are more latency and thermal sensitive it can show positive gains while also increasing efficiency.
I saw that based upon how I suspect APO operates based on post I had made on TPU around E cores shared cache and intelligently utilizing it to reduce latency, but also has a side benefit of dropping power consumption and temperatures as well that translates to power savings and/or higher performance in tandem with boosting algorithms. It could provide higher peak performance for a individual cooling restraints or longer boost duration for higher sustained performance. In either case it's a net positive.
Basically suspect Intel has mimicked disabling of CCX cores on AMD side to provide uplift within the E core cluster. It's a bit like treating each core within a cluster of E cores as a CCX if it operates as I suspect it does and then cleverly dynamically enabling or disabling them based upon the workload. It's not going to to provide performance uplift for the same reasons, but in lighter workloads that are more latency and thermal sensitive it can show positive gains while also increasing efficiency.