DRAM calculator for Zen 3

[VuurVOS]

View attachment 324085

i managed to get 3800 16 16 16 16 32 48 TRFC 304 stable by setting only these timing and let others on auto, which are pretty lose tho like tfaw 40 or TWR 26.

as soon i try to tight TRRDS TRRDL and TFAW i get error in TM5 1usmus profile, i tried first trrds 4 trrdl 6-8 tfaw 16 and get error so tried 5 - 7 - 20 and still get error, last was error 0 at cycle 7.

based on the error sheet could be TRRD related or too low vdimm, so might try raise to 1.45 sticks run pretty cool ( 41°c at full load ) i was able to get trrds 4 trrdl 8 tfaw 16 at 3600mhz.

edit : noticed tcwl was lower than tcl on auto, might try set it to 16

At 1900mhz FCLK normally you have a whole that many 5000 series processors doesn't like.
You should check for WHEA 19 errors in the eventlog or use HWInfo on the bottom of the sensors window to monitor your system for WHEA erros while using it.

Few thing you could tweak:
tRC = 42
tRRDS = 4 or 6
tRRDL= 6 or 8
tFAW = 24 (should be 4 times value of tRRDL)
tWR = 14
tCWL = 16
tRTP = 12

 

[bat33]

At 1900mhz FCLK normally you have a whole that many 5000 series processors doesn't like.
You should check for WHEA 19 errors in the eventlog or use HWInfo on the bottom of the sensors window to monitor your system for WHEA erros while using it.

Few thing you could tweak:
tRC = 42
tRRDS = 4 or 6
tRRDL= 6 or 8
tFAW = 24 (should be 4 times value of tRRDL)
tWR = 14
tCWL = 16
tRTP = 12

tried first with trrds trrdl and tfaw 4, 6, 24 and got error so tried 6, 8, 32 and still got error last was error 5 in TM5 at cycle 7 , datasheet for this error say

ive let tRDWR and tWRRD on auto which give 8 and 2

real vdimm look to be 1,43v at least thats what hwinfo report

 

[VuurVOS]

You can change ClkDrvStr AddrCmdDrvStr, CsOdtDrvStr, CkeDrvStr to 24,0,24,24. It will give you more stability.

I would have kept CLDO VDDP on 0.900v (default)
VDDG CCD can be lower than VDDG IOD.

My suggestion is:
CLDO VDDP 0.900v
VDDG CCD 0.950~1.000v
VDDG IOD 1.000~1.050v

Higher voltages doesn't always mean more stability.

 

[bat33]

You can change ClkDrvStr AddrCmdDrvStr, CsOdtDrvStr, CkeDrvStr to 24,0,24,24. It will give you more stability.

I would have kept CLDO VDDP on 0.900v (default)
VDDG CCD can be lower than VDDG IOD.

My suggestion is:
CLDO VDDP 0.900v
VDDG CCD 0.950~1.000v
VDDG IOD 1.000~1.050v

Higher voltages doesn't always mean more stability.

thank you so much

finnally fully stable with this 20 pass of TM5 1usmus profile, will do another one to confirm

next might try trrds, trrdl 4-4 and TRC 42, already great improvement 20 cycle achieved in 57min vs 1H15 before

Finnally not stable many error popped at the second test

 

[VuurVOS]

Finnally not stable many error popped at the second test

I think your tRFC is too tight. Loosen up a little bit wont hurt the perfomance much.

tRRDS = 4
tRRDL = 6
tRDRDSCL = 4
tWRWRSCL = 4
tRFC = 342
tRC = 42
tWRRD = 3

 

[bat33]

I think your tRFC is too tight. Loosen up a little bit wont hurt the perfomance much.

tRRDS = 4
tRRDL = 6
tRDRDSCL = 4
tWRWRSCL = 4
tRFC = 342
tRC = 42
tWRRD = 3

Do i keep tfaw at 16 or at 24 since tRRDL = 6 AND TFAW should be trrdl x 4.
But also ddr4 guide from github reccomend 4 - 6 - 16 so im confused

I think your tRFC is too tight. Loosen up a little bit wont hurt the perfomance much.

tRRDS = 4
tRRDL = 6
tRDRDSCL = 4
tWRWRSCL = 4
tRFC = 342
tRC = 42
tWRRD = 3

error 8 at cycle 7 with this setup , datasheet for this error say

 

[VuurVOS]

Do i keep tfaw at 16 or at 24 since tRRDL = 6 AND TFAW should be trrdl x 4.
But also ddr4 guide from github reccomend 4 - 6 - 16 so im confused

tFAW should be a multiplication of tRRDS or tRRDL. A little higher tFAW will give you more stability but it must be a multiplication of tRRDS or tRRDL value.

error 8 at cycle 7 with this setup , datasheet for this error say View attachment 324193

Can you try this?
tWTRS =4
tWTRL =12

 

[bat33]

tFAW should be a multiplication of tRRDS or tRRDL. A little higher tFAW will give you more stability but it must be a multiplication of tRRDS or tRRDL value.


Can you try this?
tWTRS =4
tWTRL =12

just tried and still got errors.

BTW these are my timings fully stable at 3600, passed many TM5 without error if this can help.

maybe i could just try these timings at 3800mhz

 

[VuurVOS]

just tried and still got errors.

View attachment 324294

BTW these are my timings fully stable at 3600, passed many TM5 without error if this can help.

maybe i could just try these timings at 3800mhz

tRC = 42
tRRDL = 6
tWTRS = 4
tWTRL =12
tRDRDSCL = 4
tWRWRSCL = 4

Must have for stability:
ClkDrvStr = 24
AddrCmdDrvStr = 0
CsOdtDrvStr = 24
CkeDrvStr = 24

This should be working fine at 3600.

 

[bat33]

tRC = 42
tRRDL = 6
tWTRS = 4
tWTRL =12
tRDRDSCL = 4
tWRWRSCL = 4

Must have for stability:
ClkDrvStr = 24
AddrCmdDrvStr = 0
CsOdtDrvStr = 24
CkeDrvStr = 24

This should be working fine at 3600.

3600 is actually stable. Thats 3800 which is not . I will try what you say thanks

 

[bat33]

tRC = 42
tRRDL = 6
tWTRS = 4
tWTRL =12
tRDRDSCL = 4
tWRWRSCL = 4

Must have for stability:
ClkDrvStr = 24
AddrCmdDrvStr = 0
CsOdtDrvStr = 24
CkeDrvStr = 24

This should be working fine at 3600.

Still not stable at 3800mhz im starting wondering if its possible. Maybe cpu imc cant handle it or even my mb. Will try push vdimm as last resort, i think soc vddp and vddg are already high enough

 

[SyWillCry]

just tried and still got errors.

-snipped-

BTW these are my timings fully stable at 3600, passed many TM5 without error if this can help.

maybe i could just try these timings at 3800mhz

I'm mildly impressed that you're able to just disable GDM and run 1T CR without adjusting any of the setup values at all. GDM on may help with your stability issues.

Also, tRCDWR can be set to 8 without any issue.
Try setting tWRRD to Auto, but setting tRDWR to 12 instead of leaving that on Auto. Temporarily high, tune that down later.
You should be able to just set tRAS to 21 to get the IMC to ignore that, removing a variable from your testing.

One major thing is that your Vsoc is incredibly low for these FCLK speeds. I've seen the average 5000 series IMC be happier with a Vsoc between 1.08 and 1.12V, rather than all the way down at 1.03V.

 

[bat33]

I'm mildly impressed that you're able to just disable GDM and run 1T CR without adjusting any of the setup values at all. GDM on may help with your stability issues.

Also, tRCDWR can be set to 8 without any issue.
Try setting tWRRD to Auto, but setting tRDWR to 12 instead of leaving that on Auto. Temporarily high, tune that down later.
You should be able to just set tRAS to 21 to get the IMC to ignore that, removing a variable from your testing.

One major thing is that your Vsoc is incredibly low for these FCLK speeds. I've seen the average 5000 series IMC be happier with a Vsoc between 1.08 and 1.12V, rather than all the way down at 1.03V.

Thanks for your feedback. So maybe my vsoc is just too low after all i will give a try then. You said to set tras to 21, is that not incredibly tight ? Or im missing something, and you think this could help the IMC ? I will give a try anyway with what you suggest. And yeah concerning gdm its set as auto and 3600 is def full stable i passed many tm5 with 1usmus profile ( 20 cycle ) to be 100% sure.
Edit : also for my 3600mhz timings primary are not set to auto but manually, this was the timings i had on my previous r5 3600, with same ram kit and same motherboard. I used ryzen dram calculator as baseline and worked with a guy called vei , i think hes from overclock.net, hes absolutely a beast and helped me a lot to find this setup

 

[bat33]

I'm mildly impressed that you're able to just disable GDM and run 1T CR without adjusting any of the setup values at all. GDM on may help with your stability issues.

Also, tRCDWR can be set to 8 without any issue.
Try setting tWRRD to Auto, but setting tRDWR to 12 instead of leaving that on Auto. Temporarily high, tune that down later.
You should be able to just set tRAS to 21 to get the IMC to ignore that, removing a variable from your testing.

One major thing is that your Vsoc is incredibly low for these FCLK speeds. I've seen the average 5000 series IMC be happier with a Vsoc between 1.08 and 1.12V, rather than all the way down at 1.03V.

finnally managed to get stable like this, look like the culpitre was VSOC, had several whea error so bumped it a bit and now look like its fully stable, passed many TM5 1usmus profile, no more whea error, except only 1 error (CPU bus/interconnect error) in 18 hours ( gaming / stress test ) i wonder if its a glitch or if im on the edge of stability, might bump soc voltage a last time, real vdimm is actually 1,424v ( reported in bios and hwinfo ) even if i set it to 1.39v in bios. once im sure im fully stable will start to tight tRRD / tFAW, then TWTR / TWR. what is sure is i get better latencys and read speed than my 3600mhz setup, so its already great