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The Zen 4c Cores in the Ryzen 8000G APUs are Clocked Slower than the Zen 4 Cores

TheLostSwede

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AMD has revealed the full specs of its upcoming Ryzen 8000G APUs and it turns out that the Zen 4c cores aren't clocking as high as the Zen 4 cores in the Ryzen 5 8500G and Ryzen 3 8300G. We should point out that the 8300G has a singular Zen 4 core and three Zen 4c Cores here, so there's no confusion. The Zen 4 cores in the 8500G have a base clock of 4.1 GHz, while the 8300G comes in at 4.0 GHz, with both of the APU's Zen 4c cores having a base clock of 3.2 GHz. Oddly enough, AMD lists the overall base clock of the 8500G as 3.5 GHz and the 8300G as 3.4 GHz with a notice that reads "Represents the average effective base frequency of all cores." AMD is in other words averaging the clock speeds of the two different cores to come up with an approximate base clock.

The Zen 4 cores in the 8500G boost up to 5 GHz, with the 8300G boosting to 4.9 GHz, whereas the Zen 4c cores in the 8500G boost up to 3.7 GHz and in the 8300G to 3.6 GHz. Here AMD doesn't provide an estimated frequency equivalent. Despite being budget models in the Ryzen 8000G-series of APUs, both SKUs get two USB4 ports with full 40 Gbps capabilities, plus a pair of USB 3.2 Gen 2 (10 Gbps) ports. Furthermore the Radeon 740M GPU will be clocked at 2.8 GHz in both APUs, but both SKUs are limited to a mere four graphics cores, whereas the Ryzen 5 8600G gets eight at the same clock speed and the Ryzen 7 8700G gets 12 at 2.9 GHz. All four APUs also support DisplayPort 2.1.



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I'm still curious to see if these chips have a lower idle power draw than the all big core variants.

All modern Ryzens idle their cores at basically 0 watts, so I'm gonna go with no, that's not where idle power draw comes from on any Ryzen. 4c have better efficiency than APU Zen 4 somewhere in the 1-2GHz range.

Rembrandt and later mobile APUs have their SOC power dialed in to a tee. On AM5 that still should not be any worse than AM4 APUs (sub 10W unless pushing hard on UCLK).
 
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All modern Ryzens idle their cores at basically 0 watts, so I'm gonna go with no, that's not where idle power draw comes from on any Ryzen. 4c have better efficiency than APU Zen 4 somewhere in the 1-2GHz range.

Rembrandt and later mobile APUs have their SOC power dialed in to a tee. On AM5 that still should not be any worse than AM4 APUs (sub 10W unless pushing hard on UCLK).

I understand that the current processors or the most modern ones work in a range of minimum and maximum frequencies... and I will take some example, which I am sure is not the most correct but it can serve as a start...

If you have a vehicle, it talks about a cruising speed, to save fuel, and extend its useful life.

In the processors I would like to know if there is any impact on the useful life, if we go from the minimum to the maximum in the working frequency from time to time, and we have those peaks all the time... in my opinion it is as if in a vehicle we are at every time accelerating and braking....

So my question is: what happens if the processors had a cruising speed... would it require less access to the maximum turbo boost? Would it extend its useful life?
 
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These are monolithic parts, derived from laptop parts. They most likely have lower idle power draw than the multichip parts.
 
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So my question is: what happens if the processors had a cruising speed... would it require less access to the maximum turbo boost? Would it extend its useful life?
On the first question - yes, but that isn’t the most efficient way to run a CPU. Race-to-idle, when the chip aggressively boosts to finish a task as fast as possible and then go to sleep proved to be better in terms of watts per workload.
On the second - maybe potentially marginally, but it is incredibly rare, nigh on impossible, for a relatively modern (read -last 15 years, if not more) to reach a point with in-spec use of actually dying while still being useful and usable performance wise. Seeing as there are still 20-25 year old workstations in use out there where anything can potentially fail and the CPUs are still fine the whole “lifespan” thing is a non-issue practically speaking.
 
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I wonder if we will se a 8700G3D version in this generation
 
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but good on amd for being transparent.

After months of not listing anything about the Zen 4C specs and being pressured by media about it, yes, they are finally being transparent.

Wasn’t this known several months ago? Not really “new(s)”.

We knew Zen 4C was going to clock lower. AMD decided to omit any of the actual clock figures from their specifications pages until early last week, so nobody knew HOW low.
 
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An average clock across the two different types of cores being reported as "base clock"... Man, this big.LITTLE thing is getting out of hand. Soon, we're gonna have a complicated formula to calculate the number of cores as well. :kookoo:
 

Count von Schwalbe

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An average clock across the two different types of cores being reported as "base clock"... Man, this big.LITTLE thing is getting out of hand. Soon, we're gonna have a complicated formula to calculate the number of cores as well. :kookoo:
C=P+(E/2)
 
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Count von Schwalbe

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"How many cores does your CPU have?"
"Well, umm..."
Or threads/2. I refuse to agree that an E-core is more than a thread.
 
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An average clock across the two different types of cores being reported as "base clock"... Man, this big.LITTLE thing is getting out of hand. Soon, we're gonna have a complicated formula to calculate the number of cores as well. :kookoo:

Only nerds enthusiasts look at those numbers anyway, but it's a lot simpler than intel true big little. It's the exact same instruction set, only gimped in cache and clock so it's easier for the scheduller to handle with existing "preferred core" algorithms, it's like you got a defective cpu with half the cores half broken but in a good way. On the other hand, Intel's solution is as we all know a mess
 
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The 3.2ghz base, 3.5ghz avg, 3.6/3.7ghz max boost back up the idea that's the general clock of space-efficient performance libraries on N4P. We kind of already knew this from Apple's M2 (3.7ghz on best bin, ~3.5ghz advertised on general bin, actually ~3.42-3.48ghz on light load and 3.3-3.4ghz in multi/single-thread on higher-core power-constrained skus), which is N5P, but still. Perhaps N4P is similar to N5P in perf, but just the additional gain of ~6% area (like regular N5->N4)...kinda like the difference between 7680->8192 (n5->n4p?).

Just speculation on my part, ofc, but kind of goes with my theory about Navi 4, which I wonder if is why AMD was cagey about exact clock speed on the 4c cores...It may show their hand wrt their architectural aim(s) moving forward.

(OT)My theory is big Navi 4 could be ~300-320w (similar to 7900xt/4080 [Super]), but size of AD104 (~300mm2). Instead of the aiming for the ~2900mhz of 5nm, it may aim for ~3.2ghz (+~11% from P version of 4/5nm) at stock and clock to around ~3.5ghz at ~375w (If, for instance, they decided to aim their design for maxing out 2x 8-pin), which makes a lot of sense to me. This goes along with the notion 24gbps RAM and current cache setup could support 8192sp at up to around ~3264mhz (personal calculation), and if you you add AMD's general RAM overclocking limitations on stock skus (+6%), they'd lock it down to ~25.6gbps (+6.66_%) and be limited to matching ram bw at ~3482mhz. Going off the power usage of 7800XT, and assuming a similar voltage(1.1v?)/amperage for the ram, it *could* theoretically clock to ~3520mhz at 375w. Sure, it'd probably only perform like something ~3.49ish (lol, ~<1%) because of bandwidth, but it'd be one hell of a tight design, and very-much fit with the ability of many aftermarket coolers, considering the potential much-higher thermal density compared to Navi 3. I could be off a small amount (or, you know, COMPLETELY WRONG), but that makes, as a general design idea, an extreme amount of sense to me, especially given these clock speeds on a finished AMD product (even if a CPU).

TLDR of it would be cards that would compete with 4060 Ti 16GB (which nVIDIA may or may not respond with a full AD106 4608sp part; 4060 Ti Super 16GB; overclocked both would theoretically have similar raster) and 4070 Ti Super stock, but the higher-end part knocking on the door of a stock 4080 when overclocked with the die size(/price?) of a AD104. This is *probably* why nVIDIA discontinued 4080, as I think it's about to look even more bad wrt value. At least with 4080 Super they will have a product Navi 4 couldn't *quite* potentially touch, and therefore demand some kind of premium. The same *could* be true of small Navi 4, which I wouldn't be surprised if is 4096sp and a similar size to AD107/4060 (~150mm2, 3072sp), perhaps allowing it to sit below the all-important $300 mark. (/OT).

While you may or may not agree with this theory (we'll know soon-enough what the reality of the situation is), it's at least interesting to ponder: "compact" CPU cores and GPUs operating on the same clock domain, if not a 1:1 ratio. I'm very curious if AMD will begin to tailor the performance of each (cpu/gpu) architecture to fit the capability of the other at the same clock and a certain ratio within their consumer desktop/laptop (or handheld) APU stack, allowing a performance level/balance across the spectrum and a completely homogeneous combined architecture combining both aspects (and perhaps AI/Tensor perf) at a predictable level, where 8 compact CPU cores and X gpu cores really is ~20-33% faster than one with 6/(x-1/4x); for example one operating at max of stock 170w TDP and the other 125w at 1.2v, tunable down to threshold voltage for mobile applications (~.3v, ~1/8 [for instance ~15-20w] power, 1/4 perf using GAA transistors?). If so, they could theoretically dictate the baseline performance not only for consoles, but everywhere else in the ecosystem as well. It would be kind of like what Apple does with the M-series, but in a very AMD sort of way.

Perhaps this is a question I should have posed at B3D. I miss those conversations, especially when an [ATi/nVIDIA] engineer would show up and chime in giving some insight into their collective thinking and direction moving forward. :wtf:
 
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An average clock across the two different types of cores being reported as "base clock"... Man, this big.LITTLE thing is getting out of hand. Soon, we're gonna have a complicated formula to calculate the number of cores as well. :kookoo:

From how it was explained to my team during an AMD briefing, Zen4c cores aren't gimped efficiency cores in the ARM or Intel sense.

Below the L2 cache they're the exact same core as the full-fat Zen4 but they can use a more compact layout. Apparently they gain some efficiencies from simply altering the layout of the die.

EDIT: Zen4c cores have less L2 cache than regular Zen4.
 
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Or threads/2. I refuse to agree that an E-core is more than a thread.
Except that Zen 4c is the same as Zen 4 just more dense and operating at a lower clock speed.

Only nerds enthusiasts look at those numbers anyway, but it's a lot simpler than intel true big little. It's the exact same instruction set, only gimped in cache and clock so it's easier for the scheduller to handle with existing "preferred core" algorithms, it's like you got a defective cpu with half the cores half broken but in a good way. On the other hand, Intel's solution is as we all know a mess
Sure, but clock speed is an exact measurable number. It shouldn't be reported as an average of clock speeds across different cores. It's unnecessary confusion.
 

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Except that Zen 4c is the same as Zen 4 just more dense and operating at a lower clock speed.
Yeah, I call those real cores. Just lower clocked, really.
 
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Except that Zen 4c is the same as Zen 4 just more dense and operating at a lower clock speed.
I think the "c" stands for cramped and capped. I'll wait for the "x" version, expanded and extreme.
 
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Only nerds enthusiasts look at those numbers anyway, but it's a lot simpler than intel true big little. It's the exact same instruction set, only gimped in cache and clock so it's easier for the scheduller to handle with existing "preferred core" algorithms, it's like you got a defective cpu with half the cores half broken but in a good way. On the other hand, Intel's solution is as we all know a mess
With AVX512 out of the picture, the instruction sets of P and E cores don't differ. The schedurer just has to be aware that there are cores with two different levels of performance, which it does.
I still maintain that for the scheduler, AMD's 4+4c configuration is a harder nut to crack than Intel's P+E. For AMD, there are four levels of performance for a thread (4 without HT, 4c without HT, 4 with HT, 4c with HT, probably in that order). For Intel, there are "just" three (P without HT, E, P with HT, probably in that order).

EDIT: Zen4c cores have less L2 cache than regular Zen4.
Not even that. The third slide here is AMD's proof that the architecture of both types is exactly the same:


There's a nice analysis of the 4c core at HWCooling.net, it goes into details I haven't seen elsewhere.
 
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After months of not listing anything about the Zen 4C specs and being pressured by media about it, yes, they are finally being transparent.



We knew Zen 4C was going to clock lower. AMD decided to omit any of the actual clock figures from their specifications pages until early last week, so nobody knew HOW low.
They keep it a secret, but they haven't hidden it from you. They hid it from the competition. I think this is normal, to not disclose sensitive information ahead of time.
 
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They keep it a secret, but they haven't hidden it from you. They hid it from the competition. I think this is normal, to not disclose sensitive information ahead of time.

??? No? It is never acceptable to hide product information that directly affects the performance from the customer. Accurate clock specifications for a CPU are not "sensitive information". Literally nobody except Apple hides that information from the consumer. Intel has ZERO problems announcing 100 new processors every year with P-Core base and boost, E-Core base and boost, boost clock power limits and duration time, and even all-core sustained boost clocks where applicable.

Nothing except the correct assessment of a processor's performance is to be gleamed from clock rate figures. That is why clock rates have ALWAYS been reported to customers. Hell, they used to print them directly on the processors!
 
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??? No? It is never acceptable to hide product information that directly affects the performance from the customer. Accurate clock specifications for a CPU are not "sensitive information". Literally nobody except Apple hides that information from the consumer. Intel has ZERO problems announcing 100 new processors every year with P-Core base and boost, E-Core base and boost, boost clock power limits and duration time, and even all-core sustained boost clocks where applicable.

Nothing except the correct assessment of a processor's performance is to be gleamed from clock rate figures. That is why clock rates have ALWAYS been reported to customers. Hell, they used to print them directly on the processors!
This is not an issue if the products haven't launched yet. But yes, it is an issue concerning Phoenix2 chips that you can already buy in laptops and handhelds, such as the 7540U.
 
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This is not an issue if the products haven't launched yet. But yes, it is an issue concerning Phoenix2 chips that you can already buy in laptops and handhelds, such as the 7540U.

7540u Was Zen4, it was replaced... with Pheonix 2 mixed Zen4/Zen4c cores as listed.
1706005138582.png


The wayback machine shows 7440u being not listed as mixed cores back in August, but it was refreshed as hybrid in November, so worst case we have 2mo without full specs.
Not great but, idk if anyone actually got their hands on a hybrid zen4/zen4c machine yet.


edit: the only confirmed Zen4/4c that seems to be in peoples hands... is the z1
https://www.amd.com/en/product/13221 and it amusingly doesn't have the clocks between 4/4c delineated.
 
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