- Joined
- Aug 15, 2016
- Messages
- 486 (0.16/day)
| Processor | Intel i7 4770k |
|---|---|
| Motherboard | ASUS Sabertooth Z87 |
| Cooling | BeQuiet! Shadow Rock 3 |
| Memory | Patriot Viper 3 RedD 16 GB @ 1866 MHz |
| Video Card(s) | XFX RX 480 GTR 8GB |
| Storage | 1x SSD Samsung EVO 250 GB 1x HDD Seagate Barracuda 3 TB 1x HDD Seagate Barracuda 4 TB |
| Display(s) | AOC Q27G2U QHD, Dell S2415H FHD |
| Case | Cooler Master HAF XM |
| Audio Device(s) | Magnat LZR 980, Razer BlackShark V2, Altec Lansing 251 |
| Power Supply | Corsair AX860 |
| Mouse | Razer DeathAdder V2 |
| Keyboard | Razer Huntsman Tournament Edition |
| Software | Windows 10 Pro x64 |
We learned last year that GDDR7 will be running at around 32 Gbps, quite an improvement of the current GDDR6X. I did some research and came up with some interesting numbers regarding bandwidth, bus width and memory clocks for the upcoming memory. I may be wrong, so please do correct me if I'm mistaken.
Most importantly, GDDR7 will be using PAM3 and NRZ signaling, while current GDDR6X uses PAM4 signaling. NRZ (non return to zero) signaling can transfer 1 bit of data per cycle, PAM4 is transfering 2 bits of data per cycle, while PAM3 will be transfering 1,5 bits per cycle. NRZ still exists in GDDR7 spec because it lowers power consumption, and will be used instead of PAM3 when there is low bandwidth need. GDDR6X clocks slower compared to other memory types because of PAM4 signaling.
So as we're currently calculating the memory effective speed on GDDR6X:
Speed = memory clock * (bit rise/fall) * QDR (quad data rate, since GDDR5) * bits per cycle
So RTX 4080 memory speed would be: 1,4 * 2 * 4 * 2 (uses PAM4) = ~22,4 Gbps for example.
Announced 32 Gbps would equal to something like: 2667 MHz memory clock, or: 2,667 * 2 * 4 * 1,5 = ~32 Gbps
A lot of people are speculating that a larger than 384-bit wide bus will be used for the next gen high end GPUs. If we take a look at memory bandwidth on a 384-bit bus, coupled with 32 Gbps effective speed, that would equal to more than 1,5 TB/s of memory bandwidth! Memory bandwidth = memory effective speed * bus width / 8 (8 bits make a byte), so 32 * 384 / 8 = 1,536 TB/s. Seems like a perfect choice for the next high end GPUs.
Even if the 256-bit bus interface will be used coupled with ~32 Gbps, it will have a memory bandwidth of 1,02 TB/s, practically the same as current RTX 4090.
Now the only question is the VRAM size. GDDR7 will still be produced using 2 GB memory chips, and later on with 3 GB in size. Maybe that's the reason Nvidia pushed back its next gen to 2025. Only way to increase the VRAM size without increasing bus width while still using 2 GB chips, would be to use socalled clamshell mode where memory chips are stacked at each side of the PCB, this however doesn't offer any memory bandwidth improvement, just doubles the memory size, and it's also cheaper for production. I believe that high end GPUs will use 3 GB chip size on a 384-bit (36 GB) wide bus, while mid-to-high tier will be on 2 GB size (24 GB) using 384-bit wide bus (something like a RTX 5080 perhaps).
Any thoughts?
Most importantly, GDDR7 will be using PAM3 and NRZ signaling, while current GDDR6X uses PAM4 signaling. NRZ (non return to zero) signaling can transfer 1 bit of data per cycle, PAM4 is transfering 2 bits of data per cycle, while PAM3 will be transfering 1,5 bits per cycle. NRZ still exists in GDDR7 spec because it lowers power consumption, and will be used instead of PAM3 when there is low bandwidth need. GDDR6X clocks slower compared to other memory types because of PAM4 signaling.
So as we're currently calculating the memory effective speed on GDDR6X:
Speed = memory clock * (bit rise/fall) * QDR (quad data rate, since GDDR5) * bits per cycle
So RTX 4080 memory speed would be: 1,4 * 2 * 4 * 2 (uses PAM4) = ~22,4 Gbps for example.
Announced 32 Gbps would equal to something like: 2667 MHz memory clock, or: 2,667 * 2 * 4 * 1,5 = ~32 Gbps
A lot of people are speculating that a larger than 384-bit wide bus will be used for the next gen high end GPUs. If we take a look at memory bandwidth on a 384-bit bus, coupled with 32 Gbps effective speed, that would equal to more than 1,5 TB/s of memory bandwidth! Memory bandwidth = memory effective speed * bus width / 8 (8 bits make a byte), so 32 * 384 / 8 = 1,536 TB/s. Seems like a perfect choice for the next high end GPUs.
Even if the 256-bit bus interface will be used coupled with ~32 Gbps, it will have a memory bandwidth of 1,02 TB/s, practically the same as current RTX 4090.
Now the only question is the VRAM size. GDDR7 will still be produced using 2 GB memory chips, and later on with 3 GB in size. Maybe that's the reason Nvidia pushed back its next gen to 2025. Only way to increase the VRAM size without increasing bus width while still using 2 GB chips, would be to use socalled clamshell mode where memory chips are stacked at each side of the PCB, this however doesn't offer any memory bandwidth improvement, just doubles the memory size, and it's also cheaper for production. I believe that high end GPUs will use 3 GB chip size on a 384-bit (36 GB) wide bus, while mid-to-high tier will be on 2 GB size (24 GB) using 384-bit wide bus (something like a RTX 5080 perhaps).
Any thoughts?
Last edited:
