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Intel Begins APX and AVX10 Enablement in Linux, Setting Foundation for Granite Rapids

AleksandarK

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Intel has begun rolling out software binaries compiled with support for upcoming Advanced Performance Extensions (APX) and Advanced Vector Extensions 10 (AVX10) instruction set extensions in their Clear Linux distribution, ahead of any processors officially supporting these capabilities launching. Clear Linux is focusing first on optimized APX and AVX10 versions of foundational software libraries like glibc and Python. This builds on Clear Linux's existing support for optimized x86-64-v2, v3, and v4 code paths, leveraging the latest microarchitectural features of each Intel CPU generation. The rationale is to prepare Clear Linux to fully leverage the performance potential of next-generation Intel Xeon server processors, code-named Granite Rapids, expected to launch later this year.

Granite Rapids will introduce AVX10.1/512 instructions as well as the new APX capabilities, which are currently not well documented implementation wise. By rolling out APX/AVX10 support in software now, Clear Linux aims to have an optimized ecosystem ready when the new processors officially ship. Initially, APX and AVX10 support is being added using the existing GCC compiler. Still, Clear Linux notes they will transition to using the upcoming GCC 14 release with more mature support for these instruction sets. The goal is to eventually have many Clear Linux packages compiled with APX/AVX10 code paths to maximize performance on future Intel CPUs. This continues Clear Linux's strategy of leveraging Intel's latest hardware capabilities in software.



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[...] as well as the new APX capabilities, which are currently not well documented [...]
Intel has published a 320-page APX specification and an overview of what will be required to support APX since it's going to touch every layer of software.
tl;dr;
  • the number of general purpose registers is doubled to 32
  • new instructions focusing on general computing
  • a more efficient instruction encoding scheme
  • compatibility with older software, APX binaries can use non-APX libraries for example
  • compilers need to be adjusted for APX
  • operating system support is needed, but it's not hard to do, especially for only allowing running of APX by users and not in the kernel itself
  • virtualization solutions need to be updated if they are to work with VMs that use APX, non-APX VMs will continue to work without modifications to hypervisors
What does that mean for users? Software should gain performance by simply recompiling with an APX-capable compiler, even if external libraries are used. Current software will continue to work like before.

Since it's a modification of the AMD64 architecture the consequences to the industry will depend on what AMD chooses to do with it (and AVX10).
 

AleksandarK

News Editor
Staff member
Joined
Aug 19, 2017
Messages
2,569 (0.97/day)
Intel has published a 320-page APX specification and an overview of what will be required to support APX since it's going to touch every layer of software.
tl;dr;
  • the number of general purpose registers is doubled to 32
  • new instructions focusing on general computing
  • a more efficient instruction encoding scheme
  • compatibility with older software, APX binaries can use non-APX libraries for example
  • compilers need to be adjusted for APX
  • operating system support is needed, but it's not hard to do, especially for only allowing running of APX by users and not in the kernel itself
  • virtualization solutions need to be updated if they are to work with VMs that use APX, non-APX VMs will continue to work without modifications to hypervisors
What does that mean for users? Software should gain performance by simply recompiling with an APX-capable compiler, even if external libraries are used. Current software will continue to work like before.

Since it's a modification of the AMD64 architecture the consequences to the industry will depend on what AMD chooses to do with it (and AVX10).
I mean implementation-wise. So we have to wait for first silicon to see what comes out of it. Edited for clarity.
 
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