Intel Xeon "Clearwater Forest" CPUs Could Utilize Direct 3D Stacking Technology

[T0@st]

Pat Gelsinger—CEO of Intel Corporation—happily revealed late last month, during an earnings call: "Clearwater Forest, our first Intel 18A part for servers has already gone into fab and Panther Lake for clients will be heading into Fab shortly." The former is positioned as the natural successor to Team Blue's many-times-delayed Xeon "Sierra Forest" (all E-Core) processor family. Intel's second generation E-core Xeon "Clearwater Forest" design is expected to launch in 2025, with a deployment of "Darkmont" efficiency-oriented cores. Official product roadmaps and patch notes have revealed basic "Clearwater Forest" information, but we have not seen many leaks. Bionic_Squash has a history of releasing strictly internal Intel presentation slides—Meteor Lake (MTL-S) desktop SKUs were uncovered last April.

Their latest discovery does not include any photo or documented evidence—Bionic_Squash's concise social media post stated: "Clearwater Forest uses 3D stacking with hybrid bonding." This claim points to the possible deployment of Foveros Direct advanced packaging—this technology was expected to be ready at some point within the second half of 2023, although a mid-December technology showcase implied that things were behind schedule. The fanciest "Clearwater Forest" Xeon processors could arrive with a maximum total of 288 E-core count (and 288 threads)—according to Wccftech analysis: "The CPU package is going to consist of a base tile on top of the interposer which is connected through a high-speed I/O, EMIB, and the cores will be sitting on the topmost layer...Foveros Direct technology will allow direct copper-to-copper bonding, enabling low resistance interconnects and around 10-micron bump pitches. Intel itself states that Foveros Direct will blur the boundary between where the wafer ends and the package begins."



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[FoulOnWhite]

Wonder if this is the same as TSMC's 3D stacking Ryzen uses, it does not seem so though, just stacked dies and not memory slapped on the top. I have been rooting for Intel for a while now, hopefully this will give them the edge they need to compete with Ryzen.

 

[wNotyarD]

Wonder if this is the same as TSMC's 3D stacking Ryzen uses, it does not seem so though, just stacked dies and not memory slapped on the top. I have been rooting for Intel for a while now, hopefully this will give them the edge they need to compete with Ryzen.

Should be Intel's own Foveros stacking tech. The only product so far that Intel used it, afaik, was Lakefield. For anything else, it is way behind schedule.