Intel Prepares Core Ultra 9 285K, Core Ultra 7 265K, and Core Ultra 5 245K Arrow Lake-S Desktop CPUs

[pressing on]

10850K
Was cheaper version of 10(only P) cores CPU.
But now core ultra 285...Hm will be premium priced because top model?

The processors being leaked here are most likely HX high end mobile rather than the Arrow Lake desktop CPUs. The reason, following your logic, is that there is a 14650HX and a 14450HX which would translate to 265K and 245K. It would make sense to have a 245K and 265K, and then rename the 14900HX as 285K rather than 290K (290K being the ARL replacement for the desktop 14900K). There are two other 14th gen HX processors, 14700HX->275K and 14500HX->255K. Using K for a processor like the 245 only makes sense as a replacement for HX.

 

[dgianstefani]

So in that example still, for example in the server and datacentre space, Intel uses more cores, more power with higher clock speeds and still loses in the majority of benchmarks.

Ah, so now you're comparing Golden Cove cores vs Zen 4?

 

[RGAFL]

Ah, so now you're comparing Golden Cove cores vs Zen 4?

What should I compare Zen 4 to then? Let me know and i'll take a look.

 

[kondamin]

Changes Chip naming scheme, keeps chipset scheme...

 

[dgianstefani]

What should I compare Zen 4 to then? Let me know and i'll take a look.

Raptor Cove cores as in the consumer and Xeon lineup for current gen CPUs (Zen 4). Like the original comment you replied to.

Instead of shifting goalposts.

 

[SL2]

10850K

I thought I could predict someones nitpicking, but I failed.
My post wasn't an attempt to list more than one CPU from each generation.

Changes Chip naming scheme, keeps chipset scheme...

Oh you think that's a new one?

 

[64K]

This new naming is so baffling and stupid

Well, it's important to keep the average consumer confused about what they are actually getting for their $$$
If it says Ultra in the name then it must be top of the line stuff.

 

[P4-630]

Well, it's important to keep the average consumer confused about what they are actually getting for their $$$
If it says Ultra in the name then it must be top of the line stuff.

At least they still use "K", so you know it's an unlocked one..

AMD's mobile CPU name scheme isn't much better either though, maybe they'll try that for desktop CPU's next.

 

[pressing on]

Changes Chip naming scheme, keeps chipset scheme...

Both got three numbers...

 

[dgianstefani]

At least they still use "K", so you know it's an unlocked one..

AMD's mobile CPU name scheme isn't much better either though, maybe the'll try that for desktop CPU's next.

I suspect the "KS" may be replaced by the x90 SKU.

I.e. 290K/KS

That or a mid cycle refresh.

If Intel can keep the naming lined up with the architecture generation, that would be good.

One thing I don't like is the APUs from AMD taking a "generation" number like the 8xxx parts. Or 13/14th gen being the same architecture.

If the first number always refers to the core architecture, would be ideal.

 

[Tek-Check]

Intel is very obviously using this rebranding to try to shake off the stigma of the turds it's been plopping out for the last god knows how many generations, but they really should've waited until Lunar/Panther Lake to do that.

Are we 100% sure that compute tile is on Intel node?

 

[Konceptz]

eh, both sides have gotten ridiculous with the naming. I'm only interested in how the removal of hyper threading is going to work out.

 

[Abaidor]

I am interested to see when they are going to drop that ridiculous limitation with PCI-E lanes and stop being so stingy. I am on a X299 platform (no gaming) and although I don't need a gazillion lanes, a few more would not hurt on the desktop.

 

[dgianstefani]

I am interested to see when they are going to drop that ridiculous limitation with PCI-E lanes and stop being so stingy. I am on a X299 platform (no gaming) and although I don't need a gazillion lanes, a few more would not hurt on the desktop.

X299 is HEDT. You are comparing to a consumer tier platform.

Bear in mind gen 4/5 lanes are 2 to 4x faster than your gen 3 lanes.

 

[P4-630]

Arrow Lake = Intel 20A

Which would be called 2nm by conventional naming standards according to most websites about Arrow Lake.

 

[Denver]

Even if Intel offers significant improvements in IPC, wouldn't this advantage be mitigated, at least to some extent, by the decrease in clockrate (inherent to the process change)?

Perhaps this could be the reason for discontinuing Hyper-Threading;

 

[Tek-Check]

There's a bombshell new article over at wccf about the instability rate of hundreds of CPUs tested.

Let's hope Intel can deliver Arrow Lake ASAP, so that the current story goes away.

 

[Sabotaged_Enigma]

K-series live on? 13th and 14th Gen currently has been un-unlocked already lol
Better cancel all K-series so settle all problems and stop blaming others.

 

[RGAFL]

Raptor Cove cores as in the consumer and Xeon lineup for current gen CPUs (Zen 4). Like the original comment you replied to.

Instead of shifting goalposts.

So using the Epyc 9554 64 core processor as Intel only goes up to 64 cores in these benchmarks at Intel Xeon Platinum 8592+ "Emerald Rapids" Linux Benchmarks Review - Phoronix it seems the Epyc wins the majority of the benchmarks, in power it's a bloodbath and it's only in the new AMX instructions there is a decent Intel lead and even there the Epyc wins a few. What goalpost am I shifting?

 

[Assimilator]

Bear in mind gen 4/5 lanes are 2 to 4x faster than your gen 3 lanes.

Lane speed is irrelevant past PCIe 4.0, we don't need 1 PCIe 5.0 lane, we need 2 PCIe 4.0 lanes. Or rather, we don't need 16 PCIe 5.0 lanes, we need 32 lanes of 4.0. This anti-consumer "HEDT" bullshit needs to end.

 

[dgianstefani]

Lane speed is irrelevant past PCIe 4.0, we don't need 1 PCIe 5.0 lane, we need 2 PCIe 4.0 lanes. Or rather, we don't need 16 PCIe 5.0 lanes, we need 32 lanes of 4.0. This anti-consumer "HEDT" bullshit needs to end.

I understand the sentiment, except more lanes means more silicon and more power draw. So it's not as simple as just adding more. There's a reason AMD went the convoluted route of twin chipsets for AM5 E series boards, which have their own downsides.

The reality is that for 90%+ of people, 16/8 lanes for GPU and 8/16 lanes for M.2 or other things is enough. Just like dual channel RAM is enough.

I'd give as an example the RTX 4090 which lost 2% of performance moving from Gen 4 x16 to Gen 4 x8 in TPU testing.

 

[N/A]

I'm not expecting all that much from Arrow Lake though. Intel keeps emphasizing 18A as the node that is supposed to enable them to return to former glory. They are barely ever even mentioning 20A and if they do then they state that it is a transitional node on the way to 18A. Going by Intel's marketing, this will be the most forgettable node ever and Arrow Lake will be a rather insignificant stepping stone on the way to 18A.

18A is a stepping stone to 16A. and that is a stepping stone to 14A. it's a +, those are the former pluses providing only 10% performance per watt. Unfortunately only post-18A nodes will be on the high NA machines. so everything until then is pretty much skippable. and hopefully for all the tiles.

 

[RGAFL]

18A is a stepping stone to 16A. and that is a stepping stone to 14A. it's a +, those are the former pluses and nobody cares about a plus providing only 10% performance per watt. Unfortunately only post-18A nodes will be on the high NA machines. so everything until then is pretty much skippable. and hopefully for all the tiles.

Exactly, theses are not whole node jumps but revisions on 2nm. We've reached the point of diminishing returns with Silicon. Whoever finds the next material to take over is going to be a very rich person (if they patent it of course),

 

[dont whant to set it"']

Headache". Ughhhbbdñ.

 

[Wirko]

Bear in mind gen 4/5 lanes are 2 to 4x faster than your gen 3 lanes.

That's great but CPUs also need better lane-splitting abilities. And I think we're going to see that in new chips, ARL or whichever is next for the desktop. Why? Because it's pretty much necessary and it costs little to implement. Also because a PCIe 5.0 x2 SSD exists, which (in that mode of operation) only makes sense if it can connect to a 5.0 x2 link on the CPU.