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AMD "Strix Point" Die Annotated, Shows Zen 5 + Zen 5c Core Layout

btarunr

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AMD on Monday launched its Ryzen AI 300 line of mobile processors based on the 4 nm "Strix Point" monolithic silicon. This chip was described by AMD as having a maximum CPU core configuration of 12-core/24-thread, which would be a neat 50% increase in core-counts over the previous generation; but there's more to it. Although "Strix Point" implements "Zen 5," not all 12 CPU cores on the silicon are the regular variant of "Zen 5." The chip physically has four "Zen 5" cores, and eight "Zen 5c" compact cores. Nemez (GPUsAreMagic) attempted to annotate the "Strix Point" die based a high-resolution photo by System360Cheese from AMD's Computex keynote; and there are some interesting findings.

The annotation reveals that the four regular "Zen 5" cores, each with a 1 MB dedicated L2 cache, share a 16 MB L3 cache. The eight "Zen 5c" cores, on the other hand, appear to share a smaller 8 MB L3 cache, in what could be a separate CCX. They each have a 1 MB L2 cache, too. The "Zen 5c" cores have the same IPC as the "Zen 5" cores when measured with common INT and FP benchmarks that don't move a lot of data; however, it could lag behind in workloads with a lot of streaming data. What's more, the previous generation "Zen 4c" cores were traditionally limited to lower frequencies than regular "Zen 4" cores, as the physically compacted cores couldn't hold onto higher core voltages. If that's the case with "Zen 5c," then what we're really looking at with "Strix Point" is an interesting hybrid core setup with eight high-IPC efficiency cores.



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I learned about the origin of Strix meaning other day. An owl that eats people from mythology.
 

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I learned about the origin of Strix meaning other day. An owl that eats people from mythology.

This is what makes the internet entertaining. I never would have thought to check into that but you're right it was a bird demon of ill omen.
 
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Here's hoping this will get a AM5 version too like Phoenix.

(or even better, Strix Halo, but that would be too good to exist on desktop and the memory configuration it uses may not be possible to do)
 
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I learned about the origin of Strix meaning other day. An owl that eats people from mythology.
ASUS' Strix-branded hardware had owl-looking designs, yes.
 
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I learned about the origin of Strix meaning other day. An owl that eats people from mythology.
Well yes but no. Unless it gets desperately hungry. -> https://en.wikipedia.org/wiki/Strix_(bird)

How exact can these annotations be anyway, given that the functional blocks must be inferred from very little available info?

Also, hopefully, that L3 will be able to work as a unified 24MB cache. Shouldn't be very hard when they are a couple millimetres apart.

What's more, the previous generation "Zen 4c" cores were traditionally limited to lower frequencies than regular "Zen 4" cores, as the physically compacted cores couldn't hold onto higher core voltages.
The Zen 4c cores were designed for a lower frequency. This means smaller, less powerful transistors on average, fewer clock domains and possibly other simplifications. They can sustain the same voltages as Zen 4 cores, they just don't benefit from them. So 5c cores differ from 5 in similar ways, and they will clock lower, absolutely.
 
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The path was pretty clear, those 8 zen5c probably occupy around the same size that 4 zen5, so for quick response and low latency (gaming), the pool of zen5 is preferred, and for low power or highly parallel and high throughput tasks is possible to fire all 12 cores with a coherent ISA giving an interesting amount of raw CPU power for a mobile device. Lunar Lake will be spanked on all metrics, without HT they are unable to fight in power, nor throughput, nor AVX code, just on quick response but with restricted power (P cores are great but undeniably a power hog).
 
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I learned about the origin of Strix meaning other day. An owl that eats people from mythology.
Real world Strix are seriously cute.

Indian Scops Owl.jpg
 
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