What is new, though, lies deep within the core structures themselves and it mostly revolves around getting more data to where it needs to be, while improving the overall efficiency of a CCD's number-crunching ability. The Zen 5 announcement is quite light on specifics, but here's what we've been told.
Each core's branch prediction unit has been tweaked to make it more accurate and spit out results quicker. This circuit is responsible for determining what instructions are most likely to be next in line for a core to process, and the rest of the core then fetches the necessary data and instructions from caches based on what the predictor calculates. If it gets it wrong, then precious cycles are wasted in getting the right information.
Thus a branch predictor that's more accurate and responds faster means the overall efficiency of the processing side of the chip is better, so nothing to complain about or criticise there.
Zen 5 also sports "wider pipelines and vectors" but without knowing exactly what AMD is referring to here, it's hard to identify what's precisely changed compared to Zen 4. Traditionally, a wider pipeline means the sequence of logic units that process instructions can handle larger data formats, but in this case, AMD probably means that Zen 5 has more pipelines (or ports, to use the correct term), more instruction schedulers, and the ability to dispatch more instruction per cycle in each core.