ASML Unveils Plans for Next-Generation "Hyper-NA" Extreme Ultraviolet Lithography

[AleksandarK]

ASML, the world's sole provider of extreme ultraviolet (EUV) lithography systems essential for manufacturing the most advanced chips, has revealed its roadmap for pushing semiconductor scaling even further. In a recent presentation, former ASML president Martin van den Brink announced the company's plans for a new "Hyper-NA" EUV technology that would succeed the High-NA EUV systems, which are just beginning to deploy. The Hyper-NA tools, still in early research stages, would increase the numerical aperture to 0.75 from High-NA's 0.55, enabling chips with transistor densities beyond the projected limits of High-NA in the early 2030s. This higher numerical aperture should reduce reliance on multi-patterning techniques that add complexity and cost.

Hyper-NA is bringing challenges of its own to commercialization. Key obstacles include light polarization effects that degrade imaging contrast, requiring polarization filters that reduce light throughput. Resist materials may also need to become thinner to maintain resolution. While leading EUV chipmakers like TSMC can likely extend scaling for several more nodes using multi-patterning with existing 0.33 NA EUV tools, Intel has adopted 0.55 High-NA to avoid these complexities. But Hyper-NA will likely become essential across the industry later this decade as High-NA's physical limits are reached. Beyond Hyper-NA, few alternative patterning solutions exist besides expensive multi-beam electron lithography, which lacks the throughput of EUV photolithography. To continue classical scaling, the industry may need to eventually transition to new channel materials with superior electron mobility properties compared to silicon, requiring novel deposition and etch capabilities.



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[Tomorrow]

Still nearly a decade away as only now are they starting to ship High-NA is numbers. First Intel and likely TSMC close by but products made using High-NA wont be released before 2026 at the earliest.

 

[bonehead123]

No thanks, I'll just wait for the Super-Duper, uber-mega, quadrupled ultra extreme ++++++++ version, heeheehee

 

[N/A]

Still nearly a decade away as only now are they starting to ship High-NA is numbers. First Intel and likely TSMC close by but products made using High-NA wont be released before 2026 at the earliest.

Intel have not mastered double patterning as well as TSMC. Intel 18A must be HighNA, soon after Arrow lake in 2025

 

[Minus Infinity]

The higher the NA the smaller the die you can produce. Already, high NA=0.55 halves the die size compared to low NA=0.33. That is not the case for multi-patterning which up until at least 2nm is still cheaper than high NA EUV and far less complex. NA=0.75 will probably halve the die size again down to 220mm^2. We will probably an the era of die stitching to make large dies.

 

[Wirko]

The higher the NA the smaller the die you can produce. Already, high NA=0.55 halves the die size compared to low NA=0.33. That is not the case for multi-patterning which up until at least 2nm is still cheaper than high NA EUV and far less complex. NA=0.75 will probably halve the die size again down to 220mm^2. We will probably an the era of die stitching to make large dies.

It's not a given that a higher NA would require halving the exposure size again. It's too far out anyway, and the technology may be a lot different than what's envisioned today when it eventually meets the real world.

Even High-NA doesn't necessarily mean that maximum die size will be halved (from 26 x 33 mm to 26 x 16.5 mm). Stitching of two exposures will be possible, apparently this has been part of the plan all along. Of course it will be costly - double the number of masks, double the exposure time and a special "stocker unit" needed to avoild doubling the wafer handling time.

For this, chipmakers must resort to a technique called stitching. This involves the process of exposing one part of a pattern with one mask and then exposing the next part with a second mask. Then, the masks are stitched together and printed on the wafer.

This is a complex process, which reduces the throughput to 135 wph. But to meet the 135 wph spec, ASML has devised a stocker unit for the system. The system exposes the first half-field on all wafers in a single lot. It stores the wafers in an onboard stocker. Then, it exposes the second half-field.

Sources: Imec, Semiengineering, Semiwiki

And a blast from the distant past for some fun. Follow the projected timeline carefully.

High NA EUV Litho May Require Larger Photomask Size

In the meantime, will the mask supply chain have six-inch EUV masks ready by 2015?

semiengineering.com

 

[Minus Infinity]

It's not a given that a higher NA would require halving the exposure size again. It's too far out anyway, and the technology may be a lot different than what's envisioned today when it eventually meets the real world.

Even High-NA doesn't necessarily mean that maximum die size will be halved (from 26 x 33 mm to 26 x 16.5 mm). Stitching of two exposures will be possible, apparently this has been part of the plan all along. Of course it will be costly - double the number of masks, double the exposure time and a special "stocker unit" needed to avoild doubling the wafer handling time.

And yet NA=0.55 has indeed halved die size to 26 x 16.5 mm. This is basic physics and the same reason why a high NA microscope lens for example has a much smaller fov than a low NA lens. If you study Fourier optics you will know why.

 

[Wirko]

And yet NA=0.55 has indeed halved die size to 26 x 16.5 mm.

The maximum die size is going to remain at 26x33. However, two partial High-NA EUV exposures will be necessary for each lithographic layer. At least the 5-6 (?) front layers that shape the transistors. For Hyper-NA, they might need to increase the number of exposures to four or maybe three or maybe not at all.

 

[Caring1]

Mega Nah.