Infinity Fabric bandwidth vs RAM bandwidth

[teck]

Inside cIOD the infinity fabric writes/reads 32 Bytes / cycle (256bits/cycle) to the Unified Memory Controller which in turns writes/reads at most 128 bits / cycles in dual memory channel to the RAM.

If everything runs at 1:1:1, how is it possible to write/read 256 bits / cycle to RAM which is only 128 bits / cycle at most in dual memory channel ?

The big Ryzen 7000 Memory and OC Tuning Guide - Infinity Fabric, EXPO, Dual-Rank, Samsung and Hynix DDR5 in Practice test with Benchmarks and Recommendations | igor´sLAB

AMD’s new Ryzen 7000 desktop CPUs, based on the Zen4 micro-architecture, still use the same chiplet design as their predecessors, with a few small but not negligible changes. Igor already gave details…

www.igorslab.de

https://www.igorslab.de/wp-content/uploads/2022/09/zen4guide_slide_4.jpg

 

[ShrimpBrime]

The new chips will run 1/2 to 1 or 1:2. Just like Intel. Which is great for bandwidth. Makes it easier to accomplish those really high DRAM speeds and maximize throughput.

The IF (AMDs *re-named?* version of Hyper Transport) controller even at 1:2 has enough bandwidth, so they are going to take advantage of that. The IF frequency will no longer have much impact on performance when you change it's frequency. Negligible I think is the word used here.

In fact, if I didn't know better, the IF has enough bandwidth to cover multi-socketed boards at the same frequency as single socketed motherboards.

 

[JWNoctis]

It does not.

On Zen 4 non-APU desktop, AFAICT (and someone, please, correct me if I got it wrong) fclk:uclk:memclk typically runs at 2:3:3. That means at 2000MHz fclk typical for the DDR5-6000 sweet spot, the absolute maximum IF bandwidth is 64GB/s read and 32GB/s/chiplet write. This number would stay the same however faster the memory itself would run, so long as fclk stays the same.

The new chips will run 1/2 to 1 or 1:2. Just like Intel. Which is great for bandwidth. Makes it easier to accomplish those really high DRAM speeds and maximize throughput.

The IF (AMDs *re-named?* version of Hyper Transport) controller even at 1:2 has enough bandwidth, so they are going to take advantage of that. The IF frequency will no longer have much impact on performance when you change it's frequency. Negligible I think is the word used here.

In fact, if I didn't know better, the IF has enough bandwidth to cover multi-socketed boards at the same frequency as single socketed motherboards.

Does it really have enough bandwidth, though? Admittedly actual impact is minor except for memory bandwidth bottlenecked applications, if my understanding is at all correct.

 

[ShrimpBrime]

It does not.

On Zen 4 non-APU desktop, AFAICT (and someone, please, correct me if I got it wrong) fclk:uclk:memclk typically runs at 2:3:3. That means at 2000MHz fclk typical for the DDR5-6000 sweet spot, the absolute maximum IF bandwidth is 64GB/s read and 32GB/s/chiplet write. This number would stay the same however faster the memory itself would run, so long as fclk stays the same.


Does it really have enough bandwidth, though? Admittedly actual impact is minor except for memory bandwidth bottlenecked applications, if my understanding is at all correct.

Bandwidth, I would hope to think so! I'm just curious if there's going to be a major sacrifice to latency.

But since the dawn of DDR... 1:1 was always the best performance. Would have the best latency.

Nope, you're right. 2:3:3. I was stuck on AM4 in my head cause that's what I have currently.

 

[TumbleGeorge]

There is definitely a need for AMD to work more on these parts of the architecture for its next generation.

 

[ShrimpBrime]

There is definitely a need for AMD to work more on these parts of the architecture for its next generation.

Well like the article said, the 2000mhz IF 1:1 never really happened. Was a total flop (imo), they had to loosen up for DDR5, but I think that's the nature of gaining frequency. Clock cycles matter, you have to be able to feed processors the data at the rate of consumption or we'd have horrible bottle-necking. I suppose pushing past 100GB/s, this is the route we have to go.

DDR5 8000Mhz sure does sound appealing. I easily run 7000mhz with Samsung chips on the competitor, would be nice to see AMD doing the same.

 

[teck]

But how is it possible that the infinity fabric writes 256 bits to the memory controller and the memory controller write only 64bit or 128 bit (dual memory channel) to RAM?