Why everyone say Zen 5 is bad ?

[oxrufiioxo]

Sure as the CPU becomes less and less important... no doubt.
Yet still the heavy masses are on 1080p, some on 1440p and far less on 4K

Also you want to see how games will scale in the future as cpu demands going up why testing at lower resolutions is important to see the outright performance difference of two chips.... That above is just a gpu benchmark.

 

[Zach_01]

Yes exactly as Zen 5 is like hardly any uplift over Zen 4. So Zen 5 3D will hardly be any improvement over Zen 4 X3D.

how exactly we know this?
I think extrapolation is not safe here

 

[oxrufiioxo]

how exactly we know this?
I think extrapolation is not very safe here

It's not but it's the best data point we have to go by.....

I actually only look at min framerate these days..... For at least the gaming portion.

 

[SL2]

Yet still the heavy masses are on 1080p, some on 1440p and far less on 4K

With much slower GPU's as well, which again makes it GPU limited.

Gaming needs cache because it needs to keep them loaded for this specific workload

We never saw what more than 8 well fed cores can do on gaming... I mean for Zen...

Someone must have checked this with a 5600X3D and a 5800X3D set at the same speed.

If some people in these last posts are right, those two should have a bigger difference than non 3D models, right? I'm not so sure about that, but obviously I don't know.

 

[Zach_01]

It's not but it's the best data point we have to go by.....

I actually only look at min framerate these days..... For at least the gaming portion.

Im saying this simple because Zen5 seems/looks like a starved design on mainstream platform.
AMD can put a hell of IOD on those EPYCs or even on Threadrippers too and charge more. At least EPYC will still sell like fresh hot cakes

 

[oxrufiioxo]

Im saying this simple because Zen5 seems/looks like a starved design on mainstream platform.
AMD can put a hell of IOD on those EPYCs or even on Threadrippers too and charge more. At least EPYC will still sell like fresh hot cakes

There is definitely a bottleneck somewhere my guess is the IF it's the least improve thing all the way back to Ryzen 3000.

 

[Wolverine2349]

That's due it being two 8 core ccd with a huge latency penalty when going through the IF.

To actually compare we'd need a 7800X3D and a another cpu with one CCD with 12 cores and X3D or a 9800X with 12 cores and 1 ccd vs the 9700X

I don't think amd or Intel will offer us am option that will work though with amd using slow ass IF and Intel now using tiles.

Well Intel using tiles, but they have all cores within the same tile on Arrow Lake. And a tile is one node. Problem is, still only 8 P cores + 16 e-cores on a single tile. I believe it is a ring bus within a tile. But Intel could have put 12 Arrow Lake P cores on the tile with the TSMC 3nm and 20A instead of 8 + 16 since 4 e-cores in a cluster takes same or a little more space than 1 P core. So Intel could get 12 P cores on Arrow Lake tile to I believe without much trouble.

Though unlike AMD, Intel at least has gotten more than 8 cores into a single node as 4 e-cores take same space or a little more than 1 P core. They just need to make the die for 12 + 0 with Arrow Lake as well. Maybe in the future they will as they also have 20A node and TSMC where as AMD only has TSMC and AMD is too cheap to go anymore than 8 cores per CCX. I believe even the Zen 5C 16 core single CCD is still multiple 8 core CCXs which still cross infinity fabric.

SO maybe Arrow Lake is also a hope, but do not see on roadmap. Unless tiles even within the same one are really that slow and bad compared to 10nm and Bartlett Lake is a better hope and actually a more rumored roadmap. But still almost 1 year wait until Q3 2025 which at soonest is July 1, 2025.

 

[SL2]

how exactly we know this?
I think extrapolation is not safe here

We would be a bit more sure about this if they launched soon. They don't.

So you're right, I don't think we can know that yet.

As long as AMD haven't launched them there's a theoretical room for improvement, even if tiny.

Also, let's not forget that we can't extrapolate from the previous generation, as TDP differences has changed. This point's to the 9800X3D getting a bigger bump over the 9700X compared to previous models.

I don't think it will make a huge difference anyway, the performance increases just gets smaller with more W at the upper end.

7700X 105 W
7800X3D 120 W

9700 W 65 W
9800X3D 120 W?

 

[igormp]

Cinebench R24 isn't available for Linux, right? At least I couldn't find it.

Nope.

That's due it being two 8 core ccd with a huge latency penalty when going through the IF.

To actually compare we'd need a 7800X3D and a another cpu with one CCD with 12 cores and X3D or a 9800X with 12 cores and 1 ccd vs the 9700X

I don't think amd or Intel will offer us am option that will work though with amd using slow ass IF and Intel now using tiles.

I don't get what you meant. In their example it's a single CCD for both 9600x and 9700x, with 2 extra cores on the latter, how would another 2~4 cores in that CCD make any further difference?

Yes exactly as vanilla Zen 5 is like hardly any uplift over vanilla Zen 4. So Zen 5 3D will hardly be any improvement over Zen 4 X3D.

Zen 5 does have some bottlenecks when it comes to front-end latency, so maybe the V-cache could alleviate that and help a lot with those bottlenecks, but I have no idea how much it'd improve things for games, and how much better it'd make it against Zen 4 with V-cache.

multiple 8 core CCXs which still cross infinity fabric.

Infra CCD access (so from one CCX to another) has no penalty on bergamo, afaik. Latency between cores in the same CCX and from ones in the same CCD, but different CCX is still the same from what I've seen.

 

[oxrufiioxo]

I don't get what you meant. In their example it's a single CCD for both 9600x and 9700x, with 2 extra cores on the latter, how would another 2~4 cores in that CCD make any further difference?

Latency to the ram seems to be the bottleneck more than how many cores a cpu has at least when it comes to ryzen. The reason the 9700X vs 9600X end up similar is likely because the 9600X has more L3 cache per core so if amd did something stupid and gave a theoretical 12 core the same cache as the 8 core sure it would likely not make a difference.

When I talk about a 12 vs 8 core single CCD I mainly mean the 50% more cache AMD should be giving it not just the core count differences.

Don't get me wrong I like the approach amd does given how their CCDs work giving them all the same cache but not giving the 8 core 33% more cache to account for it's extra cores does hurt it a bit at least when it comes to L3.

Zen 5 does have some bottlenecks when it comes to front-end latency, so maybe the V-cache could alleviate that and help a lot with those bottlenecks, but I have no idea how much it'd improve things for games, and how much better it'd make it against Zen 4 with V-cache.

That is what I am hoping.

 

[igormp]

When I talk about a 12 vs 8 core single CCD I mainly mean the 50% more cache AMD should be giving it not just the core count differences.

Yeah, I don't think we'll be seeing this anytime soon. I don't see how it'd make sense for them to have the L3 cache not be tied to the CCD itself (currently 32MB per CCD), no matter if you only have 1 or 8 cores in it.

Don't get me wrong I like the approach amd does given how their CCDs work giving them all the same cache but not giving the 8 core 33% more cache to account for it's extra cores does hurt it a bit at least when it comes to L3.

And for bergamo it's twice as bad, since it's still 32MB, but now shared between double the amount of cores.
Cache is one of the worst offenders when it comes to CPU area, having both more cores and more cache is hard.

 

[oxrufiioxo]

Yeah, I don't think we'll be seeing this anytime soon. I don't see how it'd make sense for them to have the L3 cache not be tied to the CCD itself (currently 32MB per CCD), no matter if you only have 1 or 8 cores in it.

And for bergamo it's twice as bad, since it's still 32MB, but now shared between double the amount of cores.
Cache is one of the worst offenders when it comes to CPU area, having both more cores and more cache is hard.

Oh for sure I know it has 0 chance of actually happening it's more of what I would like to see really from either cpu makers a low latency 12 core with lots of cache by the time we have it I will be saying 16 cores lmao because it will probably be 5 years from now at the soonest.

 

[igormp]

Oh for sure I know it has 0 chance of actually happening it's more of what I would like to see really from either cpu makers a low latency 12 core with lots of cache by the time we have it I will be saying 16 cores lmao because it will probably be 5 years from now at the soonest.

Zen 5c on Epyc Turin seems like it'll have 32 cores and 64MB L3 per CCD (16c/32MB L3 per CCX), so we're getting there for your core-count dreams, but cache is still lacking

 

[oxrufiioxo]

Zen 5c on Epyc Turin seems like it'll have 32 cores and 64MB L3 per CCD (16c/32MB L3 per CCX), so we're getting there for your core-count dreams, but cache is still lacking

I'd still take AMD getting the IF to run 1:1 with 8000 DDR5 though the IF has been stuck around 2000mhz for way too long imho over more cores.

 

[phanbuey]

Zen 5c on Epyc Turin seems like it'll have 32 cores and 64MB L3 per CCD (16c/32MB L3 per CCX), so we're getting there for your core-count dreams, but cache is still lacking

unless they make a version of it with 3D cache...

 

[oxrufiioxo]

unless they make a version of it with 3D cache...

Didn't they have epyc with vcache?


I believe this.
AMD EPYC™ 9004 Processors with AMD 3D V-Cache

 

[phanbuey]

Didn't they have epyc with vcache?

I don't think they've ever made the compact cores with it though -- which is weird since that would seem to be the most logical application.

 

[oxrufiioxo]

I don't think they've ever made the compact cores with it though -- which is weird since that would seem to be the most logical application.

Oic what you're saying yeah don't see why they couldn't, probably just haven't.

 

[phanbuey]

Oic what you're saying yeah don't see why they couldn't, probably just haven't.

It's like "hey we have this small core, and we can fit 16 of them on a CCD, but it really doesn't have much cache..."

but also "hey we have this process where we can put gobs of cache on top of the core..."

 

[igormp]

unless they make a version of it with 3D cache...

No can do, it seems like that C model won't have the TSVs needed for the V-cache either.

I don't think they've ever made the compact cores with it though -- which is weird since that would seem to be the most logical application.

Actually it makes no sense.
The extra cache is really helpful for CFD and other HPC applications, which really like faster clocks and are heavily memory bottlenecked. Those dense Epycs have lower clocks and less memory bandwidth per core.

Those dense Epycs are mostly meant for hylerscalers, thing cloud VM hosting and large compile farms, such workloads do not benefit from extra cache.

 

[phanbuey]

No can do, it seems like that C model won't have the TSVs needed for the V-cache either.

Actually it makes no sense.
The extra cache is really helpful for CFD and other HPC applications, which really like faster clocks and are heavily memory bottlenecked. Those dense Epycs have lower clocks and less memory bandwidth per core.

Those dense Epycs are mostly meant for hylerscalers, thing cloud VM hosting and large compile farms, such workloads do not benefit from extra cache.

IDK what kind of VMs you run but they certainly benefit from cache. The only difference is the clock, which can be adjusted and boosted btw - but otherwise it's the same core -- granted without the TSVs etc. They would need to redesign the core but two 16 core CCDs with Vcache on AM5 would sell like crazy.

Take a poll and see - "would you buy a 9990X zen 5 product with 32/64T 4.2 ghz c-class cores and 3D-Vcache"

 

[igormp]

IDK what kind of VMs you run but they certainly benefit from cache

Sorry but no:
https://www.techpowerup.com/review/amd-ryzen-7-5800x3d/12.html

And when you think about a hylerscaler that likely overprovisions their machines with shared instances, caches are going to be thrashed and made useless.

The only difference is the clock, which can be adjusted and boosted btw - but otherwise it's the same core

It can't be boosted as high as your non-dense version. Its fab process just won't tolerate clocking higher.

They would need to redesign the core but two 16 core CCDs with Vcache on AM5 would sell like crazy.

The extra cache is useless for me and the applications that I use, so I'd would rather go with a cheaper CPU that clocks higher.
Given how AM5 is bottlenecked by memory, I'd rather see a regular 8c CCD + dense 16c CCD in the consumer space, but that'd make no sense for most consumer applications, so it's just a dream like the aforementioned 12c CCD with v-cache lol
I also doubt it'd sell that much since it'd be no good for games compared to a 8c v-cache while costing way more, and for most productivity workloads it makes no sense.

 

[phanbuey]

Sorry but no:
https://www.techpowerup.com/review/amd-ryzen-7-5800x3d/12.html

And when you think about a hylerscaler that likely overprovisions their machines with shared instances, caches are going to be thrashed and made useless.

It can't be boosted as high as your non-dense version. Its fab process just won't tolerate clocking higher.

The extra cache is useless for me and the applications that I use, so I'd would rather go with a cheaper CPU that clocks higher.
Given how AM5 is bottlenecked by memory, I'd rather see a regular 8c CCD + dense 16c CCD in the consumer space, but that'd make no sense for most consumer applications, so it's just a dream like the aforementioned 12c CCD with v-cache lol
I also doubt it'd sell that much since it'd be no good for games compared to a 8c v-cache while costing way more, and for most productivity workloads it makes no sense.

I see your points - I still think you're underestimating the allure of core counts for the prosumer market.

Most gamers couldn't tell the difference between a 7600 non x and a 7950x3d if you threw a towel over the rig at 1440P -- but they will still overpay for the latter because cores and the FOMO of having the best of both worlds.

Look at these prices - the demand is high for this kind of thing.

Intel Prevails In Client CPU Sales, But Threadripper Pro Outsold Xeon Nearly 20:1 : Report | Tom's Hardware (tomshardware.com)

you push 32 cores at 3.6-4ghz zen5c into the consumer market, that chip will sell out even without vcache.

 

[igormp]

I still think you're underestimating the allure of core counts for the prosumer market.

I do consider myself a prosumer, but there are limits where raw core counts can be helpful without also increasing memory bandwidth and quantity.

Look at these prices - the demand is high for this kind of thing.

When talking about TR, remember that we're not only talking about core counts, but also way more memory channels, PCIe lanes and RDIMM support, specially since you posted a 16c version that's almost as fast as my 5950x in raw cpu perf.

you push 32 cores at 3.6-4ghz zen5c into the consumer market, that chip will sell out even without vcache.

I personally doubt it, but at this point this is just wild guessings from both of us. And if either of us had a crystal ball, we would be winning the lottery instead of discussing theoretical products from a multi billion dollar company lol

But just to be clear, are you talking about "consumer" as in AM5, or "consumer" as in threadripper? Those are totally different segments (and price ranges).

 

[ARF]

you push 32 cores at 3.6-4ghz zen5c into the consumer market, that chip will sell out even without vcache.

32 is plenty, 20-core Ryzen *900X would suffice. 24-core Ryzen *950X would suffice, too.
The thing is to have more PCIe lanes. 16 for graphics 1, 16 for graphics 2, at least 16 lanes for 4 M.2 drives, and 8 more for other devices.
That's 56 lanes PCIe required.
Make DDR5-8000 the standard, and the platform will fly...