Lattice Semiconductor Explores Buying Intel's Altera Unit

[Nomad76]

Intel Altera's FPGA unit is attracting a lot of attention in the semiconductor industry according to a recent report by Bloomberg, Lattice Semiconductor emerging as a potential buyer for the entire division. Bloomberg reports that Lattice actively works with advisers and seeks private-sector backing to support their bid. However, Intel's preference appears to be leaning toward selling only a small portion of its Altera shares instead of selling everything and this can be a decisive factor in upcoming negotiations. The potential sale has attracted interest from many outside Lattice Semiconductor, including major private equity firms such as Francisco Partners, Bain Capital, and Silver Lake Management. Qualcomm has also expressed interest in acquiring parts of Intel's design business.

Bloomberg also reports that selling just a portion of Altera's shares would likely require complex financial arrangements, while private equity firms are considering investing about $3 billion through instruments. This could result in Intel's valuation being lower than the original purchase price. Intel CEO Pat Gelsinger has indicated plans to close the Altera transaction in early 2024, with the company valuing the nearly $16.7 billion Intel paid for Altera in 2015 at approximately $17 billion. Lattice's market value of $7.48 billion is certainly smaller and can challenge Lattice's ambitions for complete control of Altera. The Intel board discussed Altera's future last week and prefers to sell only a minority stake, with a decision expected soon.



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[Daven]

Intel has to be careful from now on regarding which IP it sells. Losing rights to certain technology can lower Intel's valuation should the company ever want to be sold.

 

[L'Eliminateur]

ti's funny thinking all the truckloads of money intel wasted buying altera in the first place, it seems they never finished integrating it into "intel", think on how we could have FPGA cores on a separate die on the CPU nowadays...

AMD has done far better with xilinx in that aspect

 

[dont whant to set it"']

There is an add in a Gran Theft Auto game read along the lines " buy high ,sell low".
2cents drunken citizen out.

 

[bonehead123]

Intel CEO Pat Gelsinger has indicated plans to close the Altera transaction in early 2024

A typo ?

Or is Patsy that far behind on his calendar/schedule ?

Anyway, this transaction would probably make their financial quagmire much worse than it already is, so probably not a good idea

 

[igormp]

think on how we could have FPGA cores on a separate die on the CPU nowadays...

Like this one from 6 years ago?
But yeah, apart from this product (that I don't think got any significant traction) seems like they did fuck all with Altera.

 

[L'Eliminateur]

Like this one from 6 years ago?
But yeah, apart from this product (that I don't think got any significant traction) seems like they did fuck all with Altera.

i remember that one, but did it ever was commercialized at scale? i think it was a dead on arrival product as they never did followups. I also meant this for consumers

Imagine with a FPGA array you could have HW decoders/encoders for whatever new codecs shows and software defined accelerators, but i guess that would make the people buy even less of your new shiny thing as they can reprogram what they have.

Intel had really no business buying altera, they operate in absolute different parts of the tech spectrum with zero overlap, nothing that altera brought was of use to intel being a low volume extremely expensive high-cost high-margin product with zero use for consumers. Absolutely ZERO of altera's IP made its way into intel core products (CPU/GPU as that's pretty much all they have left after they divested themselves of f everything else, they barely do networking).

PRetty much teh same applies to AMD buying xilinx, which itr even seems they bought out of panic/spite, as again absolutely nothing of xilinx made their way into AMD products, for example a epyc or ryzen cpu with a fpga die!, or a full FPGA IO die which would allow on-the-fly reconfiguration of IFOP lanes and allow them to support faster/different memory

 

[OSdevr]

i remember that one, but did it ever was commercialized at scale? i think it was a dead on arrival product as they never did followups. I also meant this for consumers

Imagine with a FPGA array you could have HW decoders/encoders for whatever new codecs shows and software defined accelerators, but i guess that would make the people buy even less of your new shiny thing as they can reprogram what they have.

Intel had really no business buying altera, they operate in absolute different parts of the tech spectrum with zero overlap, nothing that altera brought was of use to intel being a low volume extremely expensive high-cost high-margin product with zero use for consumers. Absolutely ZERO of altera's IP made its way into intel core products (CPU/GPU as that's pretty much all they have left after they divested themselves of f everything else, they barely do networking).

PRetty much teh same applies to AMD buying xilinx, which itr even seems they bought out of panic/spite, as again absolutely nothing of xilinx made their way into AMD products, for example a epyc or ryzen cpu with a fpga die!, or a full FPGA IO die which would allow on-the-fly reconfiguration of IFOP lanes and allow them to support faster/different memory

Funny thing is both Altera and Xilinx make CPU+FPGA SOCs but they use ARM cores instead of x86.

 

[Wirko]

i remember that one, but did it ever was commercialized at scale? i think it was a dead on arrival product as they never did followups. I also meant this for consumers

Imagine with a FPGA array you could have HW decoders/encoders for whatever new codecs shows and software defined accelerators, but i guess that would make the people buy even less of your new shiny thing as they can reprogram what they have.

Intel had really no business buying altera, they operate in absolute different parts of the tech spectrum with zero overlap, nothing that altera brought was of use to intel being a low volume extremely expensive high-cost high-margin product with zero use for consumers. Absolutely ZERO of altera's IP made its way into intel core products (CPU/GPU as that's pretty much all they have left after they divested themselves of f everything else, they barely do networking).

PRetty much teh same applies to AMD buying xilinx, which itr even seems they bought out of panic/spite, as again absolutely nothing of xilinx made their way into AMD products, for example a epyc or ryzen cpu with a fpga die!, or a full FPGA IO die which would allow on-the-fly reconfiguration of IFOP lanes and allow them to support faster/different memory

Maybe AMD didn't have an exact vision of what to do with the FPGA part back in 2020-2022 but Xilinx also had networking IP. By now it seems that AMD integrated both parts quite well in their range of products (if not CPUs/GPUs). Take a look at this part of amd.com, under Accelerators:

As for integrating programmable logic into processors ... FPGAs are very inefficient area-wise and power-wise.

the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain “hard” blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.

That's from an older source from 2006 but FPGAs haven't fundamentally changed; well, they now include even larger fixed-function blocks such as CPU cores, PCIe controllers and DDR controllers.

There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this gap by including “hard” circuits such as memories and multipliers, which are very efficient when they are used. However, if these hard circuits are not used, they go wasted (including the very expensive programmable routing that surrounds the logic) and have a negative impact on logic density. In this paper we propose a new architectural concept, called shadow clusters, that seeks to mitigate this loss.

Again an older source.

At this point, we need a thorough rethink of the FPGA architecture. I imagine something like a large number of larger and smaller mostly-fixed-function blocks tied together by a small amount of programmable logic and interconnects. Could someone make that efficient enough (by die space and power consumption), yet universal enough?

Also, what is CPU microcode? It's binary data that (among other things) governs the operation of the instruction decoder to a large degree. At least it seems so but we don't even know any rough details. Therefore I assume that a significant part of the decoder is programmable logic. Lookup tables and similar stuff.

 

[L'Eliminateur]

Funny thing is both Altera and Xilinx make CPU+FPGA SOCs but they use ARM cores instead of x86.

True, i forgot about that, since forever they've had them forever.

that's another thing they bungled see, they never bothered to integrate a powerful X86 core(heck put a couple of those shitty "atom" E-cores), since those cpu+fpga are used in almost 99% of digital oscilloscopes and test gear they could've enabled much better performance or reduce the BOM by not needing a separate application processor in some higher end units

 

[Tom Yum]

PRetty much teh same applies to AMD buying xilinx, which itr even seems they bought out of panic/spite, as again absolutely nothing of xilinx made their way into AMD products

Apart from the networking line which pretty much comes entirely from Xilinx, Ryzen AI and the NPU design is entirely Xilinx IP. PCIe 6 IP will also come from the Xilinx arm when that arrives in AMD products.

FPGAs are fun, and they are great prototyping tools and for complex, low-volume designs. However they are very die area-inefficient and expensive to produce, and while configurability is a positive attribute, most end users don't need the level of configurability that a FPGA provides. If you are a large enough end user to need a specific capability from a SoC, you also probably have the scale for AMD to spin an actual custom die for you that provides that solution in a much cheaper and more area efficient manner. The only aspect is software, you could have a FPGA in a x86 SOC that can be configured to accelerate different things, but what API is software going to use to target this accelerator? Is this API configurable too? It is a struggle enough for the industry to use AI accelerators at the moment, despite how much marketing ans money is being poores into it, because software just isn't using the hardware available.

 

[OSdevr]

At this point, we need a thorough rethink of the FPGA architecture. I imagine something like a large number of larger and smaller mostly-fixed-function blocks tied together by a small amount of programmable logic and interconnects. Could someone make that efficient enough (by die space and power consumption), yet universal enough?

Also, what is CPU microcode? It's binary data that (among other things) governs the operation of the instruction decoder to a large degree. At least it seems so but we don't even know any rough details. Therefore I assume that a significant part of the decoder is programmable logic. Lookup tables and similar stuff.

FPGAs have long included huge numbers of small memory and DSP (basically FMA) blocks which are the hard circuits the papers refer to. Considering that second paper only gives a few percent improvement in area and a maximum of 12.5% I don't see that really being a game changer unless they've greatly improved the concept in the years since. A while back I read about some idea of embedding full ALUs, proper register files and other larger CPU building blocks in a reprogrammable interconnect like you say and someone patented the concept.

Microcode includes a number of things such as lookup tables, state machines and sequential programs run by embedded cores. The FPUs also use look up tables and I believe the Pentium FDIV bug was one of the main reasons Intel started making the microcode updatable (it used to be hard coded). That and the F00F bug. P5 was a fun architecture.

The only aspect is software, you could have a FPGA in a x86 SOC that can be configured to accelerate different things, but what API is software going to use to target this accelerator? Is this API configurable too? It is a struggle enough for the industry to use AI accelerators at the moment, despite how much marketing ans money is being poores into it, because software just isn't using the hardware available.

I believe OpenCL supports FPGAs and has for a while.