No, it's not. A single stick of DDR4 is 64-bit, and so is DDR5. The increased performance comes from the higher clocks. The base formula for theoretical bandwidth for ANY memory config is:
or
For dual-channel DDR4 (128-bit) at 3600MHz you'd have: 128/8 * 3600 = 57600MB/s or 57.6GB/s. Grabbing a random screenshot from aida64 with 3600MHz memory:
Pretty close, if I say so.
For DDR5 6000MHz you'd have: 128/8 * 6000 = 96000MB/s or 96GB/s. Grabbing another pic:
As you saw, the so called "quad-channel" of DDR5 makes no difference in there, what matters is the bus size, which was unchanged. Wanna know why a "quad-channel" DDR4 matches your findings of DDR5? It's because it has twice the bus size (4x64-bit = 256-bit bus).
Using a quad-channel 1950x using DDR4 at 3466MHz (weird number because that was my first result from google images):
256 (remember our bus size is double now!) / 8 *3466 = 110912, or ~111GB/s.
Extra bonus, showing the same math for a GPU, let's use a 5090 as an example: it has a 512-bit bus, with 28Gbps modules, so we have 512 / 8 * 28 = 1792GB/s, which matches perfectly its announced bandwidth.
Why not do so for an apple chip as well? My M3 Max has a 24x 16-bit controllers, so a 384-bit bus (same bus size as a 3090/4090), using LPDDR5-6400, giving us 384/8*6400=307GB/s.
Strix halo, since I mentioned it before, has a 256-bit bus (what we would call "quad-channel") with LPDDR5X-8000, giving us 256/8*8000=256GB/s of bandwidth.
Honestly I really despise the "channel" terminology for desktop since it gives way for too much ambiguity, I'd rather just use the raw bus-size. And I'm not the only one that thinks that:
x.com
For what it's worth, in that screenshot of ours with a recent CPU-Z version, it now shows "4x32-bit", which is the amount of sub-channels x the bus-size for each controller. A DDR4 platform
should show up as "2x64-bit" (not sure since I don't use windows to try it out), which in both cases leads to a total of 128-bit.