AMD to Build Zen 6 CCD on TSMC 3nm Process, Next-Gen cIOD and sIOD on 4nm

[btarunr]

AMD is rumored to be building its next-generation CCD (core complex die) that implements the "Zen 6" microarchitecture, on the 3 nm TSMC N3E foundry node. This is part of a set of rumors from ChipHell forum, which got past rumors on AMD right. Apparently, AMD will also refresh the I/O dies for its next generation process, building them on the 4 nm foundry node, likely the TSMC N4C. The TSMC N3E node offers a 20% speed improvement, over 30% power savings, and approximately 60% logic density increase over TSMC N5, whereas the TSMC N4P node that the company uses for its current "Zen 5" chiplets only clock minor increases in logic density and power over N5. The N3E node relies on EUV double-patterning to achieve its logic density increases.

Perhaps the most interesting piece of news is the new-generation I/O dies. AMD is building these on the 4 nm node, which is a significant step up from the 6 nm node its current I/O dies are built on. On the client side of things, 4 nm will enable AMD to give the new cIOD an updated iGPU, probably based on a newer graphics architecture, such as RDNA 3.5. It will also give AMD the opportunity to integrate an NPU. The company might also update its key I/O components, such as the DDR5 memory controllers, to support higher memory speeds unlocked by CUDIMMs. We don't predict any updates on the PCIe front, since AMD is expected to carry on with Socket AM5, which determines that the cIOD puts out 28 PCIe Gen 5 lanes. At best, the USB interface put out from the processor could be updated to USB4 through an on-die host controller. Over on the server side, the new-generation sIOD will bring much needed increases to the DDR5 memory speeds enabled by clock drivers.



The rumor mill also churns out something on graphics. Depending on how the Radeon RX 9000 series and RDNA 4 fare in the market, AMD could revisit the enthusiast segment with its next generation UDNA architecture that the company will make common to both graphics and compute. The company's next-generation discrete GPUs will be built around the TSMC N3E foundry node.

View at TechPowerUp Main Site | Source

 

[Mr_Engineer]

Excited for them to release a 16 or even 32 core CPUs on a single CCD + a larger 3d cache

 

[Jtuck9]

If MSI had a high end X870 ITX offering the CUDIMM support might have swung me in their favour with one eye on the future. Not sure if support on other boards is as "simple" as releasing a bios update?!

 

[3valatzy]

The company's next-generation discrete GPUs will be built around the TSMC N3E foundry node.

Let's hope so. Else, R.I.P. Radeon . .

 

[cristi_io]

I presume Zen 6 is still 2 years away for release, if it still uses AM5 socket, it is a pity, I was expecting an increase in PciExpress lanes which would need a new socket.

 

[Rightness_1]

This is weird... It's a lot of effort to build a new IO die for the last release on AM5... Unless there are no IO die changes for AM6, and they can re-use this new die on that platform too? But I'd like to think that AM6 will be quad channel, and have a few more PCiE lanes so would also need a new IO die...

 

[kondamin]

I presume Zen 6 is still 2 years away for release, if it still uses AM5 socket, it is a pity, I was expecting an increase in PciExpress lanes which would need a new socket.

a third or maybe forth memory channel sure to feed more cpu cores as the higher density on the ccd would benefit From that and a beefier igpu would to benefit from that to.

dont see the point in more than 28 pcie 5 lanes though.
it would make mother boards a lot more expensive and only a few users would benefit from it, is there anything in the consumer space that actually needs 16x PCIe 5?

 

[LittleBro]

I presume Zen 6 is still 2 years away for release, if it still uses AM5 socket, it is a pity, I was expecting an increase in PciExpress lanes which would need a new socket.

Why does Zen 6 need more PCIE lanes? For storage? There are two major things that keep Zen 5 holding back:
- shitty IOD, especially slow IMC and being too far from cores;
- PCIE 4.0 only interconnection between socket and chipset.

You can already attach as much as 4 M.2 Gen5 x4 SSDs to CPU and leave Gen5 x8 for GPU (which is still more than enough).
With PCIE Gen 5 x4 between CPU and chipset, you'd be able to attach 2 more Gen5 x2 or Gen4 x4 drives.
Do you need more? There's no need for more than 3 drives on AM5/ArrowLake-grade platform.

If you need more, especially more cores, more RAM bandwidth and more PCIE lanes, go for Threadripper or Xeon.

Personally, I'd rather have CPU without UDNA inside, meaning no GPU and no NPU at all.

 

[cristi_io]

Yes, i think it needs more PciExpress lanes, look at the MB with 2-3 M.2 ports attached to the chipset, and all connected to the Cpu with a 4 lane PciExpress 4, not even PciEx 5. Not to mention the aditional PciX lanes in the chipset.
So MB manufacturers resort to activating/deactivating ports when you plug a M.2 connected to the chipset, or Sata ports, or lanes shared between a PCiX slot-M.2.

32 lanes would be sufficient.

 

[wolf]

It isn't the technology or products themselves they really need to nail down, it's the prices and marketing - specifically the launch. Products that reviewers can easily recommend will sell and build mindshare.

Using less power, being on the best node, being ultra efficient are less important. Not to say those things can't also help of course.

Ryzen at least is building a great name for itself, especially X3D. They can probably leverage mindshare to some extent for CPUs moving forward, just don't forget the basics.

 

[Degreco]

It will also give the company a chance to update its DDR5 memory controllers

Oh yes, please use that opportunity, AMD. Besides doing the obvious (increased MT/s), the IMC needs better DDR5 stability and some of us need solid and faster 4 stick performance (not for gaming). Also, some people want better boot times with DDR5, at least they want the Intel gap closed.

And I feel like any progress in IMC and memory speed is kind of useless (like ZEN5 which promised us high speeds, then told us the 'sweet spot' was still 6.000 - 6.400 MT/s) if both the clocks of RAM and IMC are not synced up. Most people want to stay at IF 1:1 for as long as they can. Zen5 completely failed to impress in this area.

 

[LittleBro]

Yes, i think it needs more PciExpress lanes, look at the MB with 2-3 M.2 ports attached to the chipset, and all connected to the Cpu with a 4 lane PciExpress 4, not even PciEx 5. Not to mention the aditional PciX lanes in the chipset.
So MB manufacturers resort to activating/deactivating ports when you plug a M.2 connected to the chipset, or Sata ports, or lanes shared between a PCiX slot-M.2.

32 lanes would be sufficient.

At first place, why would you attach 3 M.2 drives to chipset when latency- and performance-wise it's much better option attaching them to CPU?

 

[Scotter008]

N3E is ~8% more performant and ~6% more effecient than N4P at same power/speed given that, according to TSMC,

N4P is up to ~11% more performant and ~22% more efficient than N5 at same power/same speed. N3E is up to ~20% more performant and ~30% more efficient than n5 at same power/speed.

This is worsened when considering AMD is using N4X on Zen 5, which tolerates higher voltages/clocks meant for high perf CPU. It has an additional minute uplift over it . This is not an exciting or gamechanging uplift. I believe the new IO die and rumored 12 core CCDs will do the heavy lifting on Zen 6, but we shouldn't expect 3nm GPUs (UDNA and assumingly 60 series) to be substantial improvements in the way N5 was with Ada.
The next noteworthy node shrink may be 2nm which I assume won't reach consumer till 2028 given they'll surely prioritize it in more profitable sectors such as AI compute and data center.
We have to hope for massive architectural leaps otherwise perhaps neural rendering is the next big cheat in graphics in a similar way to how we cheated lighting with raster. I'm unconvinced so far, but it's certainly grown more and more promising and likely given these developments and the reality of Blackwell.

 

[holyprof]

New IOD? Shut up and take my money. AMD reusing the old IOD is what's holding me from upgrading to 9700X right now. My current Ryzen 3700X will have to hold until then.

I'm excited to hear the rumour of 12 core CCD too. 8 cores is getting a bit short for my work, but double CCD for 16 cores is too expensive and power hungry for a mere 20-30% better productivity score. 16 core ryzen even loses to 9700X in some productivity tests. Single CCD CPU being faster in games is just a bonus for me.

So unless my platform (MoBo, CPU, RAM) dies soon, my next buy will be Zen6!

 

[Chaitanya]

If MSI had a high end X870 ITX offering the CUDIMM support might have swung me in their favour with one eye on the future. Not sure if support on other boards is as "simple" as releasing a bios update?!

As things stand right now AMD AM5 CPUs dont support clocked DDR5 RAM, maybe with new memory controller on Zen6 things may change. MSI hasnt offered mini ITX board on flagship chipset for quite sometime.

 

[3valatzy]

N3E is ~8% more performant and ~6% more effecient than N4P at same power/speed given that, according to TSMC,
N4P is up to ~11% more performant and ~22% more efficient than N5 at same power/same speed. N3E is up to ~20% more performant and ~30% more efficient than n5 at same power/speed.
This is worsened when considering AMD is using N4X on Zen 5, which tolerates higher voltages/clocks meant for high perf CPU. It has an additional minute uplift over it . This is not an exciting or gamechanging uplift. I believe the new IO die and rumored 12 core CCDs will do the heavy lifting on Zen 6, but we shouldn't EXPECT 3nm GPUs (UDNA and assumingly 60 series) to be substantial improvements in the way N5 was with Ada.
The next noteworthy node shrink may be 2nm which I assume won't reach consumer till 2028 given they'll surely prioritize it in more profitable sectors such as AI compute and data center.
We have to hope for massive architectural leaps otherwise perhaps neural rendering is the next big cheat in graphics in a similar way to how we cheated lighting with raster. I'm unconvinced so far, but it's certainly grown more and more promising and likely given these developments and the reality of Blackwell.

If this is true, N2 is a third "plus" optimisation prosess of N5, meaning it's literally the same. R.I.P. industry.

 

[Scotter008]

If this is true, N2 is a third "plus" optimisation prosess of N5, meaning it's literally the same. R.I.P. industry.

I'm assuming that N2 stacking up the prior uplifts alongside the technological boons with GAAFETs will be notable enough. For instance, TSMC states N2 should be ~25-30% less power than N3E and ~10-15% more performant at same speed/power. I'm unsure if these projections take into account GAAFETs reduced leakage, but I'm obviously no expert. Just restating what TSMC has already stated.
None of these take into consideration the added density from N3 or N2 either, which with N3 is said to be substantial. Perhaps this is what will allow 12 core CCDs since N3 will have 60% more logic density than N5? I'm not sure how the scaling works there. But as said prior it probably won't be like we're going from Ampere to Ada again.

 

[Neo_Morpheus]

And watch their marketing team butchering all the progress with a stupid name and an amateur presentation.

Not to mention, a moronic price. They need to leave the greediness to Ngreedia.

I get it, they are still recovering (believe or not) from their dark times (thank you intel illegal actions) but still, take it easy with the greediness.

 

[DutchTraveller]

There was another rumor about AMD using parallel instead of serial transmission between the chiplets in it's new mobile processors.
This lowers power-consumption and latency. And it might also allow of higher fabric frequencies which in turn allows running the RAM at higher frequencies while still at 1:1 with the fabric.
If the rumor is true it is likely that this will also be implemented in Zen6.
Combine this with CUDIMM support and we should see much higher DRAM frequencies and lower latencies (which is great for e.g. gaming).
Having lower powerdraw, epecially in idle, would also be very welcome for me.

Number of cores
I don't think more than 12 per chiplet will be viable/economic.
50% more is a nice step.

About the PCIe lanes
Current AMD MB's have very few slots. I would prefer the 5.0x16 be split into fixed x8 and 2 x4 slots (in x16 and x8 formfactors).
Fixed means that the slots will always have that many lanes. No dependent on what is plugged into the other slots.
No PCIe switches needed (which are expensive).
You can still plug SSD's into these slots using a card. The advantage is that these cards can have better cooling because there is more space.
This is more flexible and lets the user choose what to plug in and the x8 slots take up less space than M2 slots.
This way you can have 3 M2 at 5.0 speeds. The number of M2's connected to the chipset can be reduced and the lanes converted in some more x4 slots.
It would be nice if the chipset would be connected using 5.0

 

[N/A]

None of these take into consideration the added density from N3 or N2 either, which with N3 is said to be substantial. Perhaps this is what will allow 12 core CCDs since N3 will have 60% more logic density than N5? I'm not sure how the scaling works there. But as said prior it probably won't be like we're going from Ampere to Ada again.

60% for logic and 0% for sram and analog but some of that goes into the MCD or the IOD, but it's closer to 1.3X chip density for N3. and another 1.15X for N2 and then it's game over for progress.
Fake frames forever 16X MFG. 390 mm sq. UDNA with 6144 shaders 384 bit and call it a day.

 

[Wirko]

You can already attach as much as 4 M.2 Gen5 x4 SSDs to CPU and leave Gen5 x8 for GPU (which is still more than enough).
With PCIE Gen 5 x4 between CPU and chipset, you'd be able to attach 2 more Gen5 x2 or Gen4 x4 drives.

True, that needs to be upgraded (but can't be for as long as PROM21 remains the chipset for everything).

Yes, i think it needs more PciExpress lanes, look at the MB with 2-3 M.2 ports attached to the chipset, and all connected to the Cpu with a 4 lane PciExpress 4, not even PciEx 5. Not to mention the aditional PciX lanes in the chipset.

More flexibility regarding bifurcation would be even better. At least to split x4 ports from CPU into two x2 links.
AMD should also allow different chipset configurations. Zero chips, one chip, two chips, three chips, daisy-chained or not.
Also, a huge number of M.2 SSDs in a PC is not a good solution to any problem. A far better solution would be if AMD started making 8 TB SSDs for a decent price under their own brand, Nandeon. Then almost no one would need more than one or two.

 

[LittleBro]

Of course, new chipset required. There's already x4 Gen5 downlink to chipset ready on CPU-side, actually was ready even with Zen 4.

 

[Daven]

I would like to see the following:

CCD #1 : 8 performance cores at 6 GHz and 128MB of L3 on die and stacked underneath with hyperthreading

CCD #2 : 16 dense cores at 4.5 GHz and hyperthreading

iOD : Improved memory controller with 1:1 8000 MHz DDR5

 

[Wirko]

None of these take into consideration the added density from N3 or N2 either, which with N3 is said to be substantial. Perhaps this is what will allow 12 core CCDs since N3 will have 60% more logic density than N5? I'm not sure how the scaling works there. But as said prior it probably won't be like we're going from Ampere to Ada again.

They will do whatever fits their server CPUs best, and 12-core CCDs seem probable. Otherwise you have a sIOD with a giant Infinite Fabric hub with 16+ links to CCDs, which I don't think is optimal.

Regarding node shrinking, what's the SRAM scaling factor in N3 and N2 nodes? If it's bad then 48 MB of L3 and all of L2 will be very costly.

There was another rumor about AMD using parallel instead of serial transmission between the chiplets in it's new mobile processors.

I don't know what will be improved but don't think of "serial" as single wire. An IFOP link between IOD and CCD is 32 bits wide in one direction and 40 bits in the other, running at 8 GT/s. EPYCs with four CCDs have two links to each CCD.

 

[petr88]

I would like to see the following:

CCD #1 : 8 performance cores at 6 GHz and 128MB of L3 on die and stacked underneath with hyperthreading

CCD #2 : 16 dense cores at 4.5 GHz and hyperthreading

iOD : Improved memory controller with 1:1 8000 MHz DDR5

Sounds good but perfomance cores should go up to 6.5ghz even 3 years old Raptor Cove on 10nm can give 6.2ghz