I think they've actually said they are doing two things (as well as the original draw being a non-issue as you mention):
1. Lowering the power draw from the PCIe slot (they didn't say by how much or if there was a penalty for that, benching will confirm) and t
his will be enabled as standard.
and separately:
2. Adding an option to reduce overall power by "some amount" at a cost to performance that should be off-set by a claimed 3% improvement in driver performance, assuming your game of choice is one of the "uplifted" ones.
Number 1 will be the most interesting to see the results of; how much have they reduced the PCIe slot power use and is the overall use now the same just with some amount moved to the PCIe power connector on the card and how has this affected performance, in theory, on the uplifted games, performance should be 3% better than the launch reviews.
Another question is if overall TDP/TBP has changed.
We should know more in a couple of days.
For 1 this is the information we currently have, the current ref RX 480 PCB design is such that the IR3567B loop 1 (6 phases) is controlling the mosfets that supply GPU VDDC. Now the 6 phases are split 50/50 between PCI-E slot/plugs, we have independent 2 power planes, there is no "chip" on PCB that can adjust supply source to mosfets but IR3567B can do load balancing independently per phase so basically The Stilt's fix is lowering the ratio of loading capability of 3 phases supplied by PCI-E slot and shifting it to the 3 phases supplied by PCI-E plug. If there was any other method he could employ I would think he would have done that, especially with his experience and knowledge of AMD products. This is basically what I think AMD will do to reduce current/power usage from PCI-E slot. This does not effect how much power the GPU will draw or what voltage it will use, nor will it's performance be limited but what it does mean is 3 phases are being loaded more, you could depending on GPU properties/how much you push card for OC'ing hit OCP limit.
For 2 my opinion is this, PowerPlay in ROM has PowerTune table, which contains PowerLimit. These values are TDC/TDC/MPDL.
TDP: "Change TDP limit based on customer's thermal solution"
TDC: "PowerTune limit for maximum thermally sustainable current by VDDC regulator that can be supplied"
Maximum Power Delivery Limit (MPDL): "This power limit is the total chip power that we need to stay within in order to not violate the PCIe rail/connector power delivery"
These values limit GPU only not any other board elements (RAM,etc). TDC does not do any load balancing or differentiate between phases on VRM. MPDL does not differentiate between where power is drawn (ie slot/plugs). So AMD maybe implementing tweak of these settings in OS once driver load, as this is what we do when we change PL in OD/TriXX/MSI AB.
They may implement PowerTune algorithm tweak. Without delving too much into this I'll present an example based on 2 programs I experienced this on Fiji. In driver at x point they exposed a feature called "Power Efficiency". Prior to this setting being available I would adjust PL in ROM/OS to max, 3DM FS would run at max GPU clock but Heaven would show some clock dropping, with PE=Off no clock drop in Heaven. I was never reaching A/W/temps issue to make GPU drop clocks in Heaven with PE=On, so it has lead me to believe an aspect of PowerTune algorithm is being tweaked when I set PE=Off.
Just like you said I would agree it would be at a cost of performance which they are giving back in "some" titles for fix/point 2.
Now getting back to GPU properties, mainly leakage, higher leakage ASIC will draw more power. So you will have some cards not benefiting as much from the shift of load on phases to reduce PCI-E slot power usage. Like wise a higher leakage ASIC will reach PowerTune/Limit sooner under load so the owner may see more of a performance loss. IMO owners of lower leakage ASIC will benefit more from these fixes in context of "issue" and will be somewhat drawing less power as a whole at "stock".
When W1zzard tested The Stilt's tweak it drew ~10W less on PCI-E slot, which will be soon consumed by some OC'ing.
IMO the fixes are not "ideal" considering this is card which has PCI-E plug and by this I mean no disrespect to The Stilt, W1zzard and others involved with it. The ref PCB needs a redesign to be inline with what recent past AMD cards drew on PCI-E slot or to substantially reduce PCI-E slot power usage.
My apologies to members for mega long post.
Confused 
So when it {SIG} revised the spec up from the 25w to allow 75w total[12v+3.3v] where is this allowing the 12v to be over 75w not including the 3.3v already there.
