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AMD "Naples" is a 32-core Zen Based Monstrosity

I wonder why AMD is not tapping into 4P...

Also, about a Naples-class CPU for the prosumer segment, I don't believe AMD would/should introduce a different socket between the AM4 (consumer) and whatever-Naples-socket, at least for another 2 years until they get a good hold in the consumer market. For now, unless they can fit a 16- or 32-core Ryzen CPU in the AM4 socket, forget about a prosumer-class CPU from them. It would be great though...

Does anyone know if the AM4 socket has a hard power limit?
 
So if a Zeppelin die officially has 32 PCIe lanes why has Ryzen only 24 of them enabled?
Not enough pins on the socket? To reduce PCB cost? To unlock them with the first speed bump update?
 
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:D :D :D :D :D good one
 
I think there is mid step with 10, 12 and 14 cores in between depending on how they plan on segmenting the processors.

12 core is next, no midstep with 10 cores, 10 comes after 12, 16 comes after 10 and then 14.

Due to the Zen core design, 12 cores will have 48 PCI-E Lanes, for each 4 cores you can add 16 pci-e Lanes.

Additional details:
I have no clue if R3 will have 16 lanes or 32 on die as the quadcores may be defective 8 cores or how they do that, 6 cores will be a 8 core with 1 core disabled in each CCX. and will retain L3 cache and PCI-e Lanes.
We may even see 2-3 core cpu'.

Also keep in mind usable PCI-E lanes is not the lanes the CPU has, regardless of AMD and or Intel.
USB3, Southbridges/fch (if present) consume 4-8 pci-e lanes
 
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Also, about a Naples-class CPU for the prosumer segment, I don't believe AMD would/should introduce a different socket between the AM4 (consumer) and whatever-Naples-socket, at least for another 2 years until they get a good hold in the consumer market. For now, unless they can fit a 16- or 32-core Ryzen CPU in the AM4 socket, forget about a prosumer-class CPU from them. It would be great though...

They could come up with something like their own version of Intels Skulltrail which has only one board and one CPU based on SR3.
A 16 core monster for enthusiasts or prosumers and to mock Intels upcoming 12 core Extreme edition...
 
Right, forgot it's limited to CCX units...

Btw, technically, this should be able to run Crysis. I mean, Windows 10 Pro 64bit supports 2 physical CPU's (and supposedly no real limits on the cores afaik), 512GB RAM and the board has PCIe slots to stick many graphic cards in it :D
 
I wonder why AMD is not tapping into 4P...
AMD is a company with limited resources. I sure they'll get there, but I also think that's pretty specialized market. The cost of developing 4P+ might out weigh the potential profits.
 
I wonder why AMD is not tapping into 4P...

Also, about a Naples-class CPU for the prosumer segment, I don't believe AMD would/should introduce a different socket between the AM4 (consumer) and whatever-Naples-socket, at least for another 2 years until they get a good hold in the consumer market. For now, unless they can fit a 16- or 32-core Ryzen CPU in the AM4 socket, forget about a prosumer-class CPU from them. It would be great though...

Does anyone know if the AM4 socket has a hard power limit?

No need yet. 2P are the big sellers now due to the increased core counts of current processors. I used to by 4P servers for ESX when the cores were only available in quads. Now I can get way more cores in 2P.
 
It's gonna take a while for them to gain market share. Intel has been dominating server and web hosting market for past 6 years or so now.

There is also a matter of Intel platform being proven tech while Ryzen is unknown.
 
No need yet. 2P are the big sellers now due to the increased core counts of current processors. I used to by 4P servers for ESX when the cores were only available in quads. Now I can get way more cores in 2P.

You pay license per cpu socket usually, hence these 8 channel setup is going to be sweet, we're low on memory and IO, not raw cpu power in our clusters.
 
"Monstrosity"

Not sure if it was ment too but that made me laugh!
 
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I know right. I was confused by that other post.

Ok, now we're talking. Desktop CPUs for home usage alone will not bring AMD solidly into the black. But solid enterprise offerings will. There's also the mobile market to cover, but considering AMD's budget, I guess they have to move one step at a time. So far, so good.

Exactly. It will be really interesting to see how well these perform and subsequently get adopted for business. We really need AMD to gain mindshare within the enterprise sector.
 
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If it is anything like the prior gens of server chips this will not have real 8 channel memory it will probably be 4, dual channel memory controllers shared between the 8 CCX units that in one weird random circumstance can use memory across all 8 available memory channels.

AMD's PR game is strong.
 
Considering most servers are blades, and 4P blades are pretty rare, it makes sense for AMD to target the 2P market.

However, outside of linux and cloud setups, I'm wondering how a 'all the cores' approach to the server market will serve AMD considering the 2016 license change to 2 Sockets, 8 cores a socket, anymore, pay more.

That being said, considering how AMD's SMT scales better than Intels HyperThreading, I am legitimately excited for this as a server product.
 
If it is anything like the prior gens of server chips this will not have real 8 channel memory it will probably be 4, dual channel memory controllers shared between the 8 CCX units that in one weird random circumstance can use memory across all 8 available memory channels.

AMD's PR game is strong.
Maybe but there diagram shows 4x memory controller on each side of each socket ie 4per CCx cluster of two or twice(16x2per socket) what RyZen has in consumer land and way more pciex per cluster back counting it out.
 
Maybe but there diagram shows 4x memory controller on each side of each socket ie 4per CCx cluster if two or twice what RyZen has in consumer land and way more pciex per cluster back counting it out.

So it would still be dual 4 channel controllers and not an 8 channel controller.

I am sorry, but when Intel sells a core it has an FPU and an integer core and when they sell me a quad channel memory controller it is an actual quad channel controller...No tricks no halfsies none of this AMD PR nonsense. This is why people do not trust their products.
 
So it would still be dual 4 channel controllers and not an 8 channel controller.
No because each can also run two dimms so I'd guess max capacity dimms too, to reach that memory capacity and as they say specs
Doing the maths to get two tbyte on a 2p server each channel needs to run 64Gb of memory.
As for 4p think of the pciex cost in interlinks there would be few if any left over.

Me and @Eidairman have discussed this in the past , it's unclear exactly what is connected through am4s pins to me at least ,is a 390x chipset possible with more pciex and more memory controller , I don't think we have the pins for quad channel myself but they could up the lanes or bandwidth available in later chips perhaps.
 
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So it would still be dual 4 channel controllers and not an 8 channel controller.

I am sorry, but when Intel sells a core it has an FPU and an integer core and when they sell me a quad channel memory controller it is an actual quad channel controller...No tricks no halfsies none of this AMD PR nonsense. This is why people do not trust their products.

Does it matter in practice? If it works...it works.
 
So it would still be dual 4 channel controllers and not an 8 channel controller.

Most dual channel designs I know of utilise a single memory controller for each channel. That is likely an 8 channel design.
 
Better tell that to the rumor mill early testing.

I am talking about the stacked memory controller stuff. I have one of those already with my bulldozer and piledriver based server chips they have two dual channel controllers that AMD calls "quad channel" oddly every single performance benchmark places them with dual channel controllers. I am saying if this is the same thing, even if it is using a pair of quad channel controllers it will not be an octa channel setup in performance.
 
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