AMD "Naples" is a 32-core Zen Based Monstrosity

[fullinfusion]

TBH the only thing that I'd love feed back on is how well would this cpu crunch!

I only use a 8 threaded Intel chip so that's why I ask

 

[cdawall]

Ok now that I have done some more research my first hypothesis was correct.

4 dual channel memory controllers for "octa channel" memory. So memory bandwidth real world will likely be nothing like the 6 channel Intel chips.

That's not to say performance will be bad, but it is definitely not an octa channel setup as it is quoted. Not in the normal sense.

The communication between Cpus has me very very interested. 64 pcie lanes talking between each cpu is an interesting idea.

I am excited for q2 and hope I can snatched up an ES for testing.

 

[Imsochobo]

Ok now that I have done some more research my first hypothesis was correct.

4 dual channel memory controllers for "octa channel" memory. So memory bandwidth real world will likely be nothing like the 6 channel Intel chips.

That's not to say performance will be bad, but it is definitely not an octa channel setup as it is quoted. Not in the normal sense.

The communication between Cpus has me very very interested. 64 pcie lanes talking between each cpu is an interesting idea.

I am excited for q2 and hope I can snatched up an ES for testing.

Memory is probably fine.
It's not PCI-e lanes talking, it's "Data Fabric" that does the talking, they're using the PCI-E controllers for it, how is what I'm curious about.

 

[cdawall]

Memory is probably fine.
It's not PCI-e lanes talking, it's "Data Fabric" that does the talking, they're using the PCI-E controllers for it, how is what I'm curious about.

They are using 64 pcie lanes on each chip with a custom protocol (data fabric) to talk between each other.

 

[TheoneandonlyMrK]

They are using 64 pcie lanes on each chip with a custom protocol (data fabric) to talk between each other.

What's occuring here , first your sure there's half the memory channels stated for definite despite indications otherwise and no hard test cases to end the debate as you didn't get that memory capacity max =2 TB or 1 per socket.
Now your losing half the chips pciex lanes, it's 128, 64 are used just for socket to socket communication, over pciex using their infinity fabric protocol.

 

[cdawall]

What's occuring here , first your sure there's half the memory channels stated for definite despite indications otherwise and no hard test cases to end the debate as you didn't get that memory capacity max =2 TB or 1 per socket.
Now your losing half the chips pciex lanes, it's 128, 64 are used just for socket to socket communication, over pciex using their infinity fabric protocol.

Have you done zero research on this at all?

Naples will be offered as either a single processor platform (1P), or a dual processor platform (2P). In dual processor mode, and thus a system with 64 cores and 128 threads, each processor will use 64 of its PCIe lanes as a communication bus between the processors as part of AMD’s Infinity Fabric. The Infinity Fabric uses a custom protocol over these lanes, but bandwidth is designed to be on the order of PCIe. As each core uses 64 PCIe lanes to talk to the other, this allows each of the CPUs to give 64 lanes to the rest of the system, totaling 128 PCIe 3.0 again.

and look closely at the how the memory is broken down in AMD's very own picture, not to mention how the chips have magically lost 64 lanes each almost as if they are being using for the data fabric connect.

Now the ram could operate in a different manner than I am assuming, but considering they are using the same CCX units as the ryzen chip and just adding more of them I strongly doubt that it is anymore than 4 dual channel controllers teamed together for "octa channel" memory in the same exact way they have done for bulldozer/piledriver based units.

 

[TheoneandonlyMrK]

Have you done zero research on this at all?



and look closely at the how the memory is broken down in AMD's very own picture, not to mention how the chips have magically lost 64 lanes each almost as if they are being using for the data fabric connect.

Now the ram could operate in a different manner than I am assuming, but considering they are using the same CCX units as the ryzen chip and just adding more of them I strongly doubt that it is anymore than 4 dual channel controllers teamed together for "octa channel" memory in the same exact way they have done for bulldozer/piledriver based units.

I've read a lot and all the same stuff as you it seams, I'm certainly not trying to insult you but we clearly see it different , in the picture you posted it shows 64 pciex lanes coming out as useable io and just says infinity fabric between those two sockets, they tell us it uses 64 pciex lanes for interview (sigh read inter chip)socket communication over pciex using Infinity fabric protocols.
Per chip that's 128 and to be fair I disagree on the memory yeah but I'm not saying I'm definitely right just that given what they're saying it's what I believe but I won't argue that point because not many know for sure , you could be right though.

As far as it goes it would be very sensible if it did have quad channels to not use them in consumer land on a first generation chip, especially to help binning yealds.

 

[Scrizz]

I'm with
@cdawall on this one.
I'm going to wait.

 

[Jism]

Technically it's just 4x 8 full zen cores welded together with 4 memory memory controllers in total, leaving per zen module, 1 effective memory controller. And some interconnect that lets these things talk.

You really need to utilitize that to get the very best out of it, it's a different tactic then intels real quad memory controller. But since servers move lots of data, i'm sure it will be fine.

AMD has less R&D to actually develop a much better server version for ZEN, so it's sticking to a larger design then what consumers get. And by looking at those benchmarks i'm sure the chip will do fine.

Lets hope there is sufficient memory kits available for server enviroments offering decent speeds. The ZEN scales much better as memory speeds go up to 3200.

 

[JunkBear]

My [male genitalia] can't take it, it's going to EXPLODE from the blood rushing into it.

Still 3 inches of blood