Intel Could Upstage EPYC "Rome" Launch with "Cascade Lake" Before Year-end

[btarunr]

Intel is reportedly working tirelessly to launch its "Cascade Lake" Xeon Scalable 48-core enterprise processor before year-end, according to a launch window timeline slide leaked by datacenter hardware provider QCT. The slide suggests a late-Q4 thru Q1-2019 launch timeline for the XCC (extreme core count) version of "Cascade Lake," which packs 48 CPU cores across two dies on an MCM. This launch is part of QCT's "early shipment program," which means select enterprise customers can obtain the hardware in pre-approved quantities. In other words, this is a limited launch, but one that's probably enough to upstage AMD's 7 nm EPYC "Rome" 64-core processor launch.

It's only by late-Q1 thru Q2-2019 that the Xeon "Cascade Lake" family would be substantially launched, including lower core-count variants that are still 2-die MCMs. This aligns to preempt or match AMD's 7 nm EPYC family rollout through 2019. "Cascade Lake" is probably Intel's final enterprise microarchitecture to be built on the 14 nm++ node, and consists of 2-die multi-chip modules that feature 48 cores, and a 12-channel memory interface (6-channel per die); with 88-lane PCIe from the CPU socket. The processor is capable of multi-socket configurations. It will also be Intel's launch platform for substantially launching its Optane Persistent Memory product series.



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[krykry]

Honestly speaking, this doesn't feel like it'll go well. There's so many things wrong about this... A rushed response to Rome, using inferior "glued chips" (irony here) in a processor. They're already having huge problems with production lines even without this. Also adaption problems like possibly new chipset and/or socket. Also I remember interconnects for this were the inferior type...

In any case, this doesn't look like a good product launch... more like an attempt to bring in investors/appease shareholders.

 

[TheGuruStud]

No one will buy it, anyway lol. TCO?

 

[hellrazor]

Good job Intel, you're about to play yourself.

 

[Nephilim666]

So they're going to 'upstage' AMD's new 7nm 64 core chip using a new microarchitecture by producing another skylake rehash on 14nm that is essentially two 24-core dies on one package, for undoubtedly a huge amount of money. Yeah nah.

 

[Valantar]

Hasn't AMD already started shipping Rome to "select enterprise customers"?

 

[$ReaPeR$]

 

[kastriot]

Too late intel too late!
AMD 7nm
AMD Intel

 

[R0H1T]

So they're going to 'upstage' AMD's new 7nm 64 core chip using a new microarchitecture by producing another skylake rehash on 14nm that is essentially two 24-core dies on one package, for undoubtedly a huge amount of money. Yeah nah.

It's not a new uarch, it's basically SKL with a few "smeltdown" hardware fixes.

 

[Nephilim666]

It's not a new uarch, it's basically SKL with a few "smeltdown" hardware fixes.

I was referring to AMD's new microarchitecture. It's like you wrote your response before reading my whole post

 

[efikkan]

It's sad to see that nearly no one can keep their fanboyism in check and have a serious discussion about something non-AMD subjects these days. Grow up people, or go play elsewhere!

-----

Cascade Lake SP XCC means up to 28 cores, this die has been publicly known since summer last year. Intel's current roadmap shows Cooper Lake SP late 2019 and Ice Lake SP mid 2020. Cooper Lake SP will still be on 14nm, but will be on the same LGA4189 socket as Ice Lake SP, featuring "architectural improvements" and 8 memory channels. So Epyc "Rome" will compete with Cascade Lake in the beginning and then Cooper Lake later in its product cycle.

Epyc "Rome" may offer more and cheaper cores, but Intel still have faster cores. And when it comes to AVX workloads, which many enterprise workloads rely on, Intel will still have a 2× advantage over Epyc "Rome". I would expect AMD to get more of a foothold in the server market, but they don't yet have any product that will "crush" Intel's offering.

Don't forget that large shipments of Zen 2 is not right around the corner. While we could expect to see something in Q1 2019, the transition to Zen 2 will be gradual for both consumer and enterprise markets. One telling sign is that AMD launched Epyc 7000 (Zen 1) series just yesterday; it's not going to be replaced in 2-3 months. But we should look forward to Q3-Q4 2019, it will be the most interesting time for CPUs in decades; AMD will be having Zen 2 based Threadripper, Ryzen and Epyc, Intel will have Ice Lake and Cooper Lake X/SP, then we will finally start to see the effects of competition.

 

[R0H1T]

I was referring to AMD's new microarchitecture. It's like you wrote your response before reading my whole post

I didn't but yeah it's clear(er) now what you meant btw some punctuation here would've been better

AMD's new 7nm 64 core chip using a new microarchitecture, by producing another skylake rehash

 

[TheGuruStud]

It's sad to see that nearly no one can keep their fanboyism in check and have a serious discussion about something non-AMD subjects these days. Grow up people, or go play elsewhere!

-----

Cascade Lake SP XCC means up to 28 cores, this die has been publicly known since summer last year. Intel's current roadmap shows Cooper Lake SP late 2019 and Ice Lake SP mid 2020. Cooper Lake SP will still be on 14nm, but will be on the same LGA4189 socket as Ice Lake SP, featuring "architectural improvements" and 8 memory channels. So Epyc "Rome" will compete with Cascade Lake in the beginning and then Cooper Lake later in its product cycle.

Epyc "Rome" may offer more and cheaper cores, but Intel still have faster cores. And when it comes to AVX workloads, which many enterprise workloads rely on, Intel will still have a 2× advantage over Epyc "Rome". I would expect AMD to get more of a foothold in the server market, but they don't yet have any product that will "crush" Intel's offering.

Don't forget that large shipments of Zen 2 is not right around the corner. While we could expect to see something in Q1 2019, the transition to Zen 2 will be gradual for both consumer and enterprise markets. One telling sign is that AMD launched Epyc 7000 (Zen 1) series just yesterday; it's not going to be replaced in 2-3 months. But we should look forward to Q3-Q4 2019, it will be the most interesting time for CPUs in decades; AMD will be having Zen 2 based Threadripper, Ryzen and Epyc, Intel will have Ice Lake and Cooper Lake X/SP, then we will finally start to see the effects of competition.

A new platform with insane power consumption is pointless. No amount of deflection disproves that. And intel is not going to have faster cores outside of AVX 512, which will probably be a wash considering AMD has more cores to throw at it with better power consumption and still cheaper product.

 

[ShurikN]

Intel can only compete in name and theory. In practice it's a 350W, water cooled mostrosity

 

[qcmadness]

It's sad to see that nearly no one can keep their fanboyism in check and have a serious discussion about something non-AMD subjects these days. Grow up people, or go play elsewhere!

-----

Cascade Lake SP XCC means up to 28 cores, this die has been publicly known since summer last year. Intel's current roadmap shows Cooper Lake SP late 2019 and Ice Lake SP mid 2020. Cooper Lake SP will still be on 14nm, but will be on the same LGA4189 socket as Ice Lake SP, featuring "architectural improvements" and 8 memory channels. So Epyc "Rome" will compete with Cascade Lake in the beginning and then Cooper Lake later in its product cycle.

Epyc "Rome" may offer more and cheaper cores, but Intel still have faster cores. And when it comes to AVX workloads, which many enterprise workloads rely on, Intel will still have a 2× advantage over Epyc "Rome". I would expect AMD to get more of a foothold in the server market, but they don't yet have any product that will "crush" Intel's offering.

Don't forget that large shipments of Zen 2 is not right around the corner. While we could expect to see something in Q1 2019, the transition to Zen 2 will be gradual for both consumer and enterprise markets. One telling sign is that AMD launched Epyc 7000 (Zen 1) series just yesterday; it's not going to be replaced in 2-3 months. But we should look forward to Q3-Q4 2019, it will be the most interesting time for CPUs in decades; AMD will be having Zen 2 based Threadripper, Ryzen and Epyc, Intel will have Ice Lake and Cooper Lake X/SP, then we will finally start to see the effects of competition.

https://www.techpowerup.com/img/ARoRoGwRmG9TaJ2X.jpg

https://www.techpowerup.com/249450/amd-zen-2-ipc-29-percent-higher-than-zen#g249450-1

AMD Zen: 4x 128-bit FPU
AMD Zen 2: 4x 256-bit FPU (double FP width)

Unless Intel could do 4x 512-bit AVX, how could Intel maintain 2x advantage AVX workload over Zen 2?

 

[TheGuruStud]

Intel can only compete in name and theory. In practice it's a 350W, water cooled mostrosity

No company in their right mind would buy a single one. They have to power that swine AND pay to cool it lol (don't think many are doing ambient cooling).

 

[Fizzle bomber]

It's sad to see that nearly no one can keep their fanboyism in check and have a serious discussion about something non-AMD subjects these days. Grow up people, or go play elsewhere!

-----

Cascade Lake SP XCC means up to 28 cores, this die has been publicly known since summer last year. Intel's current roadmap shows Cooper Lake SP late 2019 and Ice Lake SP mid 2020. Cooper Lake SP will still be on 14nm, but will be on the same LGA4189 socket as Ice Lake SP, featuring "architectural improvements" and 8 memory channels. So Epyc "Rome" will compete with Cascade Lake in the beginning and then Cooper Lake later in its product cycle.

Epyc "Rome" may offer more and cheaper cores, but Intel still have faster cores. And when it comes to AVX workloads, which many enterprise workloads rely on, Intel will still have a 2× advantage over Epyc "Rome". I would expect AMD to get more of a foothold in the server market, but they don't yet have any product that will "crush" Intel's offering.

Don't forget that large shipments of Zen 2 is not right around the corner. While we could expect to see something in Q1 2019, the transition to Zen 2 will be gradual for both consumer and enterprise markets. One telling sign is that AMD launched Epyc 7000 (Zen 1) series just yesterday; it's not going to be replaced in 2-3 months. But we should look forward to Q3-Q4 2019, it will be the most interesting time for CPUs in decades; AMD will be having Zen 2 based Threadripper, Ryzen and Epyc, Intel will have Ice Lake and Cooper Lake X/SP, then we will finally start to see the effects of competition.

Intel might still have faster single core performance. But don't forget that we are talking about 7nm process and some pretty good architectural improvements. So if Intel gives 5% performance over AMD then I won't count that as faster at all. Things would get totally uncomfortable for Intel when 64 cores of AMD goes against it on multithreaded workloads and that too being far cheaper in price as in the past. Intel is Indeed going to be in trouble...they are already troubled looking at the 9900x which isn't that great considering the thermals, price. Their only advantage was with the optimized process that deliver higher clocks and we can see that a 9900x is just a 8700K with more cores using better manufacturing process to get more clocks. Although very fast, it is just a desperate attempt to defend against AMD onslaught.

 

[efikkan]

AMD Zen: 4x 128-bit FPU
AMD Zen 2: 4x 256-bit FPU (double FP width)

Unless Intel could do 4x 512-bit AVX, how could Intel maintain 2x advantage AVX workload over Zen 2?

SIMD units usually don't work that way, they are often split up for power gating and balancing. Zen 2 will have 2× 256-bit MUL and 2× 256-bit ADD (and one FMA??)
Skylake-X/SP have 2× 512-bit MUL, 2× 512-bit ADD and 2× 512-bit FMA. Except for uncertain details of the execution ports, this is ~2× max throughput.

 

[qcmadness]

SIMD units usually don't work that way, they are often split up for power gating and balancing. Zen 2 will have 2× 256-bit MUL and 2× 256-bit ADD (and one FMA??)
Skylake-X/SP have 2× 512-bit MUL, 2× 512-bit ADD and 2× 512-bit FMA. Except for uncertain details of the execution ports, this is ~2× max throughput.

Totally wrong.

Zen could do 2x 128-bit MUL and 2x 128-bit ADD, could be fused to 2x 128-bit FMA

https://www.anandtech.com/show/1059...t-2-extracting-instructionlevel-parallelism/4
The FP Unit uses four pipes rather than three on Excavator, and we are told that the latency in Zen is reduced as well for operations (though more information on this will come at a later date). We have two MUL and two ADD in the FP unit, capable of joining to form two 128-bit FMACs, but not one 256-bit AVX.

Doubling that would be 2x 256-bit FMA or 2x 256-bit ADD + 2x256-bit MUL

https://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/4
On the defensive and not afraid to speak their mind about the competition, Intel likes to emphasize that AMD's Zen core has only two 128-bit FMACs, while Intel's Skylake-SP has two 256-bit FMACs and one 512-bit FMAC. The latter is only useable with AVX-512. On paper at least, it would look like AMD is at a massive disadvantage, as each 256-bit AVX 2.0 instruction can process twice as much data compared to AMD's 128-bit units. Once you use AVX-512 bit, Intel can potentially offer 32 Double Precision floating operations, or 4 times AMD's peak.

For Skylake SP. It has 2x512-bit FMA (Port 0+1 and Port 5) or 2x512-bit ADD / MUL.

 

[Flanker]

IMO the people who actually buy hardware in these segments should know about which chip suit their application better, better than most of us anyway. They will definitely know which architecture can do their computations more efficiently

 

[qcmadness]

IMO the people who actually buy hardware in these segments should know about which chip suit their application better, better than most of us anyway. They will definitely know which architecture can do their computations more efficiently

Intels server will still be the king of transaction-type server such as database server.

For server with less dependent threads such as Virtual Machines, AMD servers will shine versus Intel servers.

 

[Vya Domus]

For Skylake SP. It has 2x512-bit FMA (Port 0+1 and Port 5) or 2x512-bit ADD / MUL.

Skylake SP's AVX advantage is much more frail than people realize. AMD's choice to still not Include AVX 512 (which by the way it is still not a widely used extension) but rather improve their existing implementation avoided a massive power consumption issue (which Intel clearly has a problem with). Rome wont crush Intel's 48 core offering, but it will be damn close and will likely use less power.

IMO the people who actually buy hardware in these segments should know about which chip suit their application better, better than most of us anyway.

You'd be surprised. Though it may certainly not be prevalent, lack of knowledge and false preconceived notions aren't exactly extinct in that professional environment.

 

[Aquinus]

If Cascade Lake is still a huge monolithic die, I don't think there is anything for AMD to worry about considering either prices and/or yields are likely to be garbage.

 

[mak1skav]

The word Upstage in the title needs some quotes too.

 

[hat]

So they're going to 'upstage' AMD's new 7nm 64 core chip using a new microarchitecture by producing another skylake rehash on 14nm that is essentially two 24-core dies on one package, for undoubtedly a huge amount of money. Yeah nah.

My thoughts exactly...