Intel Could Upstage EPYC "Rome" Launch with "Cascade Lake" Before Year-end

[sergionography]

No one will buy it, anyway lol. TCO?

If only what you say was true. For countless times we have seen AMD coming up with competitive or even superior products, yet consumers still end up getting intel. This is especially true in the professional field as most professionals just continue to stick to the "known" brand they are used to rather than actually doing research every time they have a project. It will take AMD about 5 to 10 years of constant product superiority in servers and high performance before this segment notices.

 

[DeathtoGnomes]

Intel might still have faster single core performance. But don't forget that we are talking about 7nm process and some pretty good architectural improvements. So if Intel gives 5% performance over AMD then I won't count that as faster at all. Things would get totally uncomfortable for Intel when 64 cores of AMD goes against it on multithreaded workloads and that too being far cheaper in price as in the past. Intel is Indeed going to be in trouble...they are already troubled looking at the 9900x which isn't that great considering the thermals, price. Their only advantage was with the optimized process that deliver higher clocks and we can see that a 9900x is just a 8700K with more cores using better manufacturing process to get more clocks. Although very fast, it is just a desperate attempt to defend against AMD onslaught.

I agree, plus we all know Intel will charge atleast 33% more than EPYC for that 5%.

 

[HD64G]

Imho, in most use cases Rome CPUs will easily surpass Intel's offerings in the server segments. And most possibly, Intel in order to reduce security problems in their CPUs will disable HT for their server cpus and thus Rome's 128 threads will go against the 56 "glued" threads of the CL offerings. With almost half the power consumption.

 

[HTC]

Imho, in most use cases Rome CPUs will easily surpass Intel's offerings in the server segments. And most possibly, Intel in order to reduce security problems in their CPUs will disable HT for their server cpus and thus Rome's 128 threads will go against the 56 "glued" threads of the CL offerings. With almost half the power consumption.

If i'm not mistaken, this 48 core chip does NOT have HT, due to power constraints.

 

[nemesis.ie]

You'd be surprised. Though it may certainly not be prevalent, lack of knowledge and false preconceived notions aren't exactly extinct in that professional environment.

For sure, I still hear "senior" IT people (managers and engineers) in large organisations talking about "Wintel" servers. And just meaning Windows as opposed to Linux.

 

[ValenOne]

Totally wrong.

Zen could do 2x 128-bit MUL and 2x 128-bit ADD, could be fused to 2x 128-bit FMA

https://www.anandtech.com/show/1059...t-2-extracting-instructionlevel-parallelism/4
The FP Unit uses four pipes rather than three on Excavator, and we are told that the latency in Zen is reduced as well for operations (though more information on this will come at a later date). We have two MUL and two ADD in the FP unit, capable of joining to form two 128-bit FMACs, but not one 256-bit AVX.

Doubling that would be 2x 256-bit FMA or 2x 256-bit ADD + 2x256-bit MUL

https://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/4
On the defensive and not afraid to speak their mind about the competition, Intel likes to emphasize that AMD's Zen core has only two 128-bit FMACs, while Intel's Skylake-SP has two 256-bit FMACs and one 512-bit FMAC. The latter is only useable with AVX-512. On paper at least, it would look like AMD is at a massive disadvantage, as each 256-bit AVX 2.0 instruction can process twice as much data compared to AMD's 128-bit units. Once you use AVX-512 bit, Intel can potentially offer 32 Double Precision floating operations, or 4 times AMD's peak.

For Skylake SP. It has 2x512-bit FMA (Port 0+1 and Port 5) or 2x512-bit ADD / MUL.

According to https://en.wikichip.org/wiki/amd/microarchitectures/zen
ZEN v1 has two 128 bit FMUL/FMA and two 128bit FADD units.


From https://developer.amd.com/wordpress/media/2013/12/55723_SOG_Fam_17h_Processors_3.00.pdf
Read page PDF's page 32 of 45, FMA (fused multiply–add) operation uses MUL pipes only i.e. Pipes 0 and 1. Pipes 2 and 3 has FADD operations. As a software developer (in one of software companies revealed with ROME's PR) , I don't completely believe journalist until I see proper source documentation.

ROME doubles FPU throughput.

"Totally wrong" is somewhere else.

 

[qcmadness]

According to https://en.wikichip.org/wiki/amd/microarchitectures/zen
ZEN v1 has two 128 bit FMUL/FMA and two 128bit FADD units.


From https://developer.amd.com/wordpress/media/2013/12/55723_SOG_Fam_17h_Processors_3.00.pdf
Read page PDF's page 32 of 45, FMA (fused multiply–add) operation uses MUL pipes only i.e. Pipes 0 and 1. Pipes 2 and 3 has FADD operations. As a software developer (in one of software companies revealed with ROME's PR) , I don't completely believe journalist until I see proper source documentation.

ROME doubles FPU throughput.

"Totally wrong" is somewhere else.

My apologies here and with efikkan.
But I stand that Skylake-SP could not provide double the AVX performance than Zen 2 unless using AVX-512 only scenario.

 

[FordGT90Concept]

Intel can only compete in name and theory. In practice it's a 350W, water cooled mostrosity

Liquid cooling does make a lot of sense for mainframes. I suspect Intel would only make this product if they had a very specific customer in mind (e.g. LNLL super computer).

 

[Melvis]

Am I missing something here or? intel is going to upstage AMD with a lesser core count CPU? 48 vs 64cores.......how exactly is this upstaging again?

 

[HTC]

Am I missing something here or? intel is going to upstage AMD with a lesser core count CPU? 48 vs 64cores.......how exactly is this upstaging again?

Add to that, it's supposedly 48 cores without HT VS 64 cores with SMT and, to top it all off, Intel's supposedly has a much higher TDP ...

 

[Deleted member 158293]

Intel scores an "E" for effort on this one based on their marketing, but is completely outclassed by AMD in engineering.

 

[HTC]

Apparently i was wrong with Intel's 48 core chip not having HT (or the following was faked):

 

[Valantar]

Apparently i was wrong with Intel's 48 core chip not having HT (or the following was faked):

Well, there's nothing saying there couldn't be ES chips out there with all kinds of non-final features, but I'd think Intel would leave that to their server/enterprise customers to configure to themselves. Disabling HT in BIOS is trivial, after all, and should be so even on crazy server motherboards. And while Spectre/Meltdown/all rest are only relevant when HT is enabled, I'm guessing most server vendors are either knowingly willing to take that risk or able to disable HT by their own volition. Of course, it might just be disabled by the BIOS by default, but open to being enabled, if Intel wants to be safe but leave options open.

Still, no matter the impressive achievement that this no doubt is, it comes off as ... disappointing compared to the competition based off a rather substantive list of complaints. First off, there was Intel's smarmy "glued-together" comment from last year, that while correctly pointed out to be an actual technical term and not just derogatory, still came off as that - and was clearly intended to be so. And now here they are doing the same thing, just in a way that is more "glued-together" than AMD's solution, as the silicon was never intended for this implementation in the first place. Then there's the fact that this (again!) necessitates a new socket, leaving Intel with four concurrent sockets (115whatever, 2011, 3647 and whatever this is, >9000 I guess), all of which are relevant in the enterprise/server space. That's a mess if I ever saw one. This, again, speaks to Intel not being forward-looking whatsoever, and shows how utterly unplanned this was when the silicon was designed. Then there's the heat and power that this will no doubt produce. Of course, Epyc Rome will no doubt be able to produce quite a bit of heat, but given how hot Intel's 18-core chips run, this is worrying. Of course, the clocks are lowered, and with a giant socket the IHS will also be gigantic, but still ... Cooling this will not be fun. Then there's this not having hardware fixes for the major security flaws in Intel's arch.

All in all: too little, too late, too flung-together-at-the-last-minute. Not impressed, even if they get it out the door before AMD (which, well, is doubtful given that Rome according to reports is already shipping to select partners).

 

[FordGT90Concept]

Imho, in most use cases Rome CPUs will easily surpass Intel's offerings in the server segments. And most possibly, Intel in order to reduce security problems in their CPUs will disable HT for their server cpus and thus Rome's 128 threads will go against the 56 "glued" threads of the CL offerings. With almost half the power consumption.

There's absolutely nothing suggesting Hyperthreading is disabled on it. Hyperthreading is a cheap (from silicon perspective) means to process more threads. Only the cheapest of the cheap Xeons (aka "Bronze") have no Hyperthreading.

 

[HTC]

There's absolutely nothing suggesting Hyperthreading is disabled on it. Hyperthreading is a cheap (from silicon perspective) means to process more threads. Only the cheapest of the cheap Xeons (aka "Bronze") have no Hyperthreading.

TDP constraints: it's still unknown @ this point in time.

I've seen rumors indicating Intel would launch the 48 core processor without HT.

This cinebench i posted in post #29 result could have been faked just as easily as this one.

 

[FordGT90Concept]

Intel has 28c/56t Xeons (8180 and 8180F). Why did they choose 24c/48t to MCM? Lower TDP and smaller package. Again, absolutely nothing to suggest Hyperthreading is disabled.

I doubt it's running at 2.5 GHz especially if the 350w TDP is to be believed. It's probably closer to 2 GHz.

 

[Vya Domus]

Intel has 28c/56t Xeons (8180 and 8180F). Why did they choose 24c/48t to MCM? Lower TDP and smaller package. Again, absolutely nothing to suggest Hyperthreading is disabled.

I doubt it's running at 2.5 GHz especially if the 350w TDP is to be believed. It's probably closer to 2 GHz.

They did compare their offering to a EPYC system with SMT disabled. There has to be a reason for that.

Or maybe the reason is that it's just not very impressive, even with HT.

 

[HTC]

Intel has 28c/56t Xeons (8180 and 8180F). Why did they choose 24c/48t to MCM? Lower TDP and smaller package. Again, absolutely nothing to suggest Hyperthreading is disabled.

I doubt it's running at 2.5 GHz especially if the 350w TDP is to be believed. It's probably closer to 2 GHz.

And what is the CPU TDPs of a two-socket system with these CPUs?

Intel can have a single 24 core CPU have "low enough" TDP but they are putting a couple of these in a single socket: it's obvious that, even with lower frequencies, the TDP will skyrocket and removing HT is a sure-way to minimize TDP, not to mention many of the security issues Intel is currently facing will be negated by HT removal.

 

[FordGT90Concept]

They did compare their offering to a EPYC system with SMT disabled. There has to be a reason for that.

Or maybe the reason is that it's just not very impressive, even with HT.

It's marketing slides. Their job is bending the truth to make their product look as good as possible.

 

[R0H1T]

Intel has 28c/56t Xeons (8180 and 8180F). Why did they choose 24c/48t to MCM? Lower TDP and smaller package. Again, absolutely nothing to suggest Hyperthreading is disabled.

I doubt it's running at 2.5 GHz especially if the 350w TDP is to be believed. It's probably closer to 2 GHz.

The chips are also rumored to be Xeon Phi replacements i.e. AVX512 monsters with not more than 96 (real) cores in a 2S system. The HT part depends on lots of factors like TDP, clock speeds (HT could force lower clocks) as well as future "smeltdown" mitigation.

 

[FordGT90Concept]

And what is the CPU TDPs of a two-socket system with these CPUs?

8180? 205w each.

The chips are also rumored to be Xeon Phi replacements i.e. AVX512 monsters with not more than 96 (real) cores in a 2S system. The HT part depends on lots of factors like TDP, clock speeds (HT could force lower clocks) as well as future "smeltdown" mitigation.

We're talking about a $20,000 processor here. The only Xeons without Hyperthreading are <$500. If they couldn't offer a 48c processor without Hyperthreading, they simply wouldn't offer the processor at all and instead, choose a smaller package to MCM (e.g. 16c/32t 8153).

The only 24c/48t packages for candidates in the 48c/96t processor are golden samples. They've likely been binning them for over a year now.

 

[HTC]

8180? 205w each.

Do you honestly expect Intel to launch a 48 core CPU with 410W TDP? Even disabling HT, TDP will still be around 350W, or so we're guessing.

The clock speeds would have to be significantly lowered to enable a "more friendly" TDP but that would be a problem VS Rome 64c / 128t so i seriously doubt Intel would do that.

 

[FordGT90Concept]

Intel's customers wouldn't consider 48c/48t next to AMD's 64c/128t.

As I said before, mainframes should move towards liquid cooling because liquid is easier to manage in clusters. We don't have TDP figures for Rome either--it might be liquid cooled as well.

 

[HTC]

Intel's customers wouldn't consider 48c/48t next to AMD's 64c/128t.

As I said before, mainframes should move towards liquid cooling because liquid is easier to manage in clusters. We don't have TDP figures for Rome either--it might be liquid cooled as well.

But Intel HAS to show something and, apparently, Intel's CPU is "made" to work with a 4 socket system, so it will have 192 cores VS AMD 128c / 256t in a dual socket system: depending on the speeds involved, it's possible Intel's CPUs could "outrun" AMD's in many workloads, so it can still be competitive, but it will be so @ double the sockets.

 

[Vya Domus]

4 of these on a board ? May God have mercy on whoever has the job of designing cooling solutions.