No PCIe Gen5 for "Raphael," Says Gigabyte's Leaked Socket AM5 Documentation

[TheoneandonlyMrK]

Intel had PCIe 5.0 devices in 2019, not that it matters, since there's nothing to plug in to it, just like their upcoming desktop platform.

Newsroom Home

Intel Newsroom home page

newsroom.intel.com

I really doubt it'll be any faster, but you're refusing to understand what I've mentioned, so I give up. Bye bye.



AMD is a board member of the PCI-SIG, since PCIe is what everything from a Raspberry Pi 4 CM to Annapurna's custom server chips for Amazon uses.
Unless there's an industry wide move to something else, I think we're going to keep using PCIe for now.
We're obviously going to be switching to something different at one point, but we're absolutely not at a point where PCIe is getting useless in most devices.
I'm sure we'll see very high-end server platforms switch to something else in the near future, but a regular PC doesn't have multiple CPU sockets or FPGA cards for real-time computational tasks, so the requirements for a wider bus simply isn't there yet.
CCIX is unlikely to ever end up in consumer platforms, but Gen-Z/CXL might (AMD is in both camps). I also have a feeling, as with so many past standards, that whatever becomes the de facto standard, will end up being managed by the PCI-SIG. They've taken over a lot of standards, like PCIe, M.2 etc.

PCI-SIG - Wikipedia

en.wikipedia.org

Fair enough but it's not impossible to run two protocols over one connection and bus either.

 

[docnorth]

Many people on this thread are traveling between interfaces, lanes, cost, speeds etc and miss the practical point. PCIe 4 will be the almost skipped generation (@AnarchoPrimitiv somehow pointed this out), mostly because Intel was unable to move from 14nm lithography and decided to jump directly to PCIe 5. RL is just a parenthesis for marketing reasons. Actually we are stuck, like Intel, on PCIe 3 for over a decade and we think it’s normal, because our NVMe is faster than sata SSD. But storage and RAM are much larger now, some newer games won’t even fit in a small SSD and consequently faster interfaces and connections will (as always) become a necessity. After a transition interval, late 2022 or early 2023 the adoption of PCIe 5 will be almost eruptive Imo.

Epyc Genoa will have PCIe 5.0, and that's actually where it's needed, but PCIe 5.0 seems to me to be a completely unnecessary marketing point for a consumer platform at this time (or even in a years time) that only has the potential to drive up costs. The overwhelming majority of people still don't even have a second gen PCIe 4.0 NVMe SSD, and we can all agree that the difference between a PCIe 3.0 NVMe SSD and a 4.0 SSD is imperceptible. This article implies that when AMD made the switch to PCIe 4.0, it is comparable to this situation, when that's hardly the case considering PCIe 3.0 was released in 2010 and the first PCIe 4.0 motherboards were released in 2019....that's nine years, whereas PCIe 4.0 has only been around for approximately two years and hasn't even been fully saturated yet by a GPU.

Maybe indirectly, but you nailed it. PCIe 4 will be the almost skipped (or lost) generation.

 

[Mussels]

Being on a Gen 4 system here, i really dont think Gen 5 is needed yet... i could change to Gen 3 and not notice a damn thing

If staying on Gen 4 lets them avoid things like x570s chipset fan, it's the right choice

 

[TheLostSwede]

Many people on this thread are traveling between interfaces, lanes, cost, speeds etc and miss the practical point. PCIe 4 will be the almost skipped generation (@AnarchoPrimitiv somehow pointed this out), mostly because Intel was unable to move from 14nm lithography and decided to jump directly to PCIe 5. RL is just a parenthesis for marketing reasons. Actually we are stuck, like Intel, on PCIe 3 for over a decade and we think it’s normal, because our NVMe is faster than sata SSD. But storage and RAM are much larger now, some newer games won’t even fit in a small SSD and consequently faster interfaces and connections will (as always) become a necessity. After a transition interval, late 2022 or early 2023 the adoption of PCIe 5 will be almost eruptive Imo.


Maybe indirectly, but you nailed it. PCIe 4 will be the almost skipped (or lost) generation.

Sorry, but have you even looked at what Intel announced? They have no less than 12 PCIe 4.0 lanes coming from the chipset, so how is this skipping PCIe 4.0?
With the distance of PCIe 5.0 lanes being almost half of PCIe 4.0 lanes before you need redrivers, it's not likely it'll be widely adopted on all interfaces, especially on consumer motherboards.

 

[TumbleGeorge]

Sorry, but have you even looked at what Intel announced? They have no less than 12 PCIe 4.0 lanes coming from the chipset, so how is this skipping PCIe 4.0?
With the distance of PCIe 5.0 lanes being almost half of PCIe 4.0 lanes before you need redrivers, it's not likely it'll be widely adopted on all interfaces, especially on consumer motherboards.

If chipset z890 for PC(after LGA 1700 z690 and z790) will be with PCIe 5.0 in 2023-2024, PCIe 4.0 will be most skipped from Intel in high class chipset. 2021 in z590 to z890 in 2023 or 2024 is only 2-3 years.
Oops in z590 PCIe is 3.0...Haha! That's mean most short transfer to PCIe 5.0 or direct jump from PCIe 3.0 to PCIe 5.0 in chipsets PCIe lines.

 

[TheLostSwede]

If chipset z890 for PC(after LGA 1700 z690 and z790) will be with PCIe 5.0 in 2023-2024, PCIe 4.0 will be most skipped from Intel in high class chipset. 2021 in z590 to z890 in 2023 or 2024 is only 2-3 years.
Oops in z590 PCIe is 3.0...Haha! That's mean most short transfer to PCIe 5.0 or direct jump from PCIe 3.0 to PCIe 5.0 in chipsets PCIe lines.

I believe we'll see a mix of PCIe buses moving forward, as the limitation in distance from the root complex to the physical slot is going to get shorter and shorter as speed increases, unless we're moving away to something everyone entirely different over time.

 

[TumbleGeorge]

I believe we'll see a mix of PCIe buses moving forward, as the limitation in distance from the root complex to the physical slot is going to get shorter and shorter as speed increases, unless we're moving away to something everyone entirely different over time.

Yes chipset is more close to part of PCIe slots(include to part of PCIe to M.2/SATA which are on long distance from CPU) and SATA ports also to USB and other internal connectors which has not ports. When PCIe in chipset go to version 5.0 this will be very important.

 

[bencrutz]

Sorry, but have you even looked at what Intel announced? They have no less than 12 PCIe 4.0 lanes coming from the chipset, so how is this skipping PCIe 4.0?
With the distance of PCIe 5.0 lanes being almost half of PCIe 4.0 lanes before you need redrivers, it's not likely it'll be widely adopted on all interfaces, especially on consumer motherboards.

pcie 5.0 motherboard would need retimers to achieve the same thing pcie 4.0 motherboard did with redrivers.
add atx12vo to the mix, we can expect them to be helluva expensive

 

[Valantar]

Many people on this thread are traveling between interfaces, lanes, cost, speeds etc and miss the practical point. PCIe 4 will be the almost skipped generation (@AnarchoPrimitiv somehow pointed this out), mostly because Intel was unable to move from 14nm lithography and decided to jump directly to PCIe 5. RL is just a parenthesis for marketing reasons. Actually we are stuck, like Intel, on PCIe 3 for over a decade and we think it’s normal, because our NVMe is faster than sata SSD. But storage and RAM are much larger now, some newer games won’t even fit in a small SSD and consequently faster interfaces and connections will (as always) become a necessity. After a transition interval, late 2022 or early 2023 the adoption of PCIe 5 will be almost eruptive Imo.


Maybe indirectly, but you nailed it. PCIe 4 will be the almost skipped (or lost) generation.

Define "skipped", please. If CPUs and chipsets move to later generations (with backwards compatibility), but attached devices don't jump past it, will it be skipped? Clearly not. Just because platform holders seem intent on pushing an I/O standard with near zero realistic benefits to users doesn't mean the rest of the industry will follow

Will we see massively overpriced ultra-premium PCIe 5.0 m.2 drives? Sure. Will they be tangibly better than 4.0, or supplant them in the market? Highly unlikely - they'll be a push for higher ASPs and more premium branding. As @TheLostSwede says, the overall industry is likely to slowly move to adopting 4.0 for AICs and controllers, but this is a process that takes time. The main reasons for it taking time is design and implementation costs, as well as potentially limiting customer bases if the goal is to limit lane counts. PCIe 5.0 does zero to alleviate any of this, and arguably exacerbates things instead - moving controllers and AICs to 5.0 will be more expensive than moving them to 4.0, and given how few things actually need the bandwidth, there's less incentive for OEMs to take on that cost. I agree that we'll likely see USB4 and 10GbE move to 4.0 in relatively short order (i.e. over the next couple of years), but even for high-bandwidth uses like that, 5.0 is going to take a lot of time to make any kind of sense. That leaves SSDs (as I said, likely, but rather pointless unless someone invents flash that doesn't need as much parallelism, which ... yeah, that isn't happening any time soon) and GPUs (which also don't need the bandwidth, and will arguably need less bandwidth with adoption of DirectStorage and any competing APIs).

PCIe 5.0 makes perfect sense for datacenters where more bandwidth can always be put to use, and more accelerators, controllers, NICs and AICs per CPU is always better. But for end users? I doubt we'll see even a single 5.0 product with any tangible benefits from that interface in the next 3-4 years.

 

[TumbleGeorge]

pcie 5.0 motherboard would need retimers

Where is retimers?

 

[docnorth]

Sorry, but have you even looked at what Intel announced? They have no less than 12 PCIe 4.0 lanes coming from the chipset, so how is this skipping PCIe 4.0?
With the distance of PCIe 5.0 lanes being almost half of PCIe 4.0 lanes before you need redrivers, it's not likely it'll be widely adopted on all interfaces, especially on consumer motherboards.

I guess we all did read that Intel's first PCIe 5 implementation for consumers is incomplete at best, but the fact remains. PCIe 4 came way too late and after 2023 it will mostly survive as the budget option. Let's not forget e.g. that last year PCIe 4 GPUs helped AMD to beat Intel in gaming performance and that next-gen flagship GPUs are rumored to be 2-2,5 times more powerful.

P.S. Right now I don't even care about PCIe 4, but before the end of 2022 I must build or buy a new office PC, it's an obligatory 5 year cycle (actually it will already be delayed). After those 5 years the PCs find their way home, I know it sounds selfish, but the offsprings are more than happy with a GPU upgrade. That's why I'll follow the PCIe 5 and DDR5 path and cost won't be a big issue. Due to covid I'll get a subsidy (I hope it's the right term for business financial aid) and like always a tax write-off.

 

[Valantar]

Where is retimers?

... they wouldn't show up in a block diagram like this - they're a part of the signal path. They might not be necessary for the first PCIe slot, as that might be close enough to the CPU to avoid them. But anything below would need retimers, just like 4.0 motherboards need redrivers. You don't see those on I/O block diagrams either, as they aren't part of the featureset, but of the signal path. Block diagrams don't list ancillary components.

 

[TheLostSwede]

Where is retimers?

You're aware that is a block diagram, right? Redrivers and retimers never appear on those, much like third party controllers don't show up here, be it USB, SATA or something else.

What Intel clearly did right here, was to put a much fatter pipe to the chipset, not only by going to PCIe 4.0 (as DMI is pretty much PCIe), but also by moving to eight lanes, so compared to the previous generation, this is quadrupling the available bandwidth between the chipset and the CPU. However, it looks like it's needed as well, since one interesting thing that's being revealed here is that Intel seems to be ready to push 5Gbps Ethernet, in addition to more and faster USB ports and obviously those 12 PCIe 4.0 lanes, which we'll see Thunderbolt or USB4 hang off of.

 

[docnorth]

... they wouldn't show up in a block diagram like this - they're a part of the signal path. They might not be necessary for the first PCIe slot, as that might be close enough to the CPU to avoid them. But anything below would need retimers, just like 4.0 motherboards need redrivers. You don't see those on I/O block diagrams either, as they aren't part of the featureset, but of the signal path. Block diagrams don't list ancillary components.

Even if a re-timer is needed for the first PCIe slot too, it's not a big deal. Re-timers are already used on PCIe 4 interface without problems, the cost is reasonable and will decrease further, the latency is measured in ns (I'm not 100% certain about this) and there is no signal loss.

 

[TheLostSwede]

Even if a re-timer is needed for the first PCIe slot too, it's not a big deal. Re-timers are already used on PCIe 4 interface without problems, the cost is reasonable and will decrease further, the latency is measured in ns (I'm not 100% certain about this) and there is no signal loss.

Uhm, you might be wrong about the cost being reasonable.
An eight lane PCIe 4.0 retimer from TI costs US$23.50 each, if you buy 1k units.

https://www.ti.com/product/DS160PT801#order-quality

A four channel PCIe 4.0 redriver is much more reasonable at under $4 each at 1k, but you might end up needing a few of those dotted around a board.

https://www.ti.com/product/SN75LVPE4410#order-quality

 

[iO]

Reasonable choice. PCIe 5.0 makes little sense for most consumers in the foreseeable future.
Also avoids the need for expensive 8 layer PCBs which will be pretty much mandatory for PCIe 5.0...

 

[ARF]

The title of the article is wrong - it is not for Raphael in particular, but for the AM5 motherboards as a whole.

AMD might skip PCIe 5 for the consumers, altogether.

 

[TumbleGeorge]

Uhm, you might be wrong about the cost being reasonable.
An eight lane PCIe 4.0 retimer from TI costs US$23.50 each, if you buy 1k units.

https://www.ti.com/product/DS160PT801#order-quality

A four channel PCIe 4.0 redriver is much more reasonable at under $4 each at 1k, but you might end up needing a few of those dotted around a board.

https://www.ti.com/product/SN75LVPE4410#order-quality

Looks like much cheaper just to use PCB with better wires.

 

[Solid State Soul ( SSS )]

i think this is a good thing, AMD not rushing for pci 5 just yet means cheaper boards and gives them time to implement it right in the future, unlike the actively cooled pci4 chipsets that spread a lot of controversy

 

[TheLostSwede]

Looks like much cheaper just to use PCB with better wires.

That's not how it works though.
For one, PCB's don't have wires, they have multiple layers with copper traces, but you can't simply make those traces thicker or wider, it's not enough to improve the signal. For PCIe 5.0 we're talking transfer rates of ~4GB/sec, per direction, per lane, so any kind of interference is going to mess that up.
Yes, the board makers shifted to more advanced PCB materials with PCIe 4.0, but this isn't directly related to the copper traces, but rather to the material the PCB is made from, to try and reduce interference and noise.
Keep in mind that one retimer isn't going to be enough if you want all slots on a motherboard to be PCIe 5.0, you're most likely going to need a couple of them, so that's $50 or more on the retail price of a motherboard for something that's unlikely to benefit any consumer for at least the next five years.
The average ATX size X570 board seem to use three to five redrivers, depending on the design. That alone is $12 or more, which I'm expecting will still be required in combination with the retimers.
The redrivers have improved since the X570 chipset launched, as it seems early redrivers could only handle two PCIe lanes, whereas more recent ones seems to be able to handle up to four PCIe lanes, so that might allow for some cost savings.

Some interesting bits here as well, which shows the difference between a redriver and a retimer.

PCI Express® Retimers vs. Redrivers: An Eye-Popping Difference | PCI-SIG

pcisig.com

Love engineering groups that don't use metric...
Anyhow, this shows that moving from PCIe 4.0 to 5.0 cuts about 40% of the trance length due to signal loss.
Right now, high-end motherboards are using low-loss PCBs.
Keep in mind that this is trace length, which is much longer than the distance of the slot from the chipset/CPU.

Retimers to the Rescue Webinar: PCI-SIG® Q&A | PCI-SIG

pcisig.com

 

[ARF]

i think this is a good thing, AMD not rushing for pci 5 just yet means cheaper boards and gives them time to implement it right in the future, unlike the actively cooled pci4 chipsets that spread a lot of controversy

Until that time comes, PCIe 6 will be ready, so AMD skipping PCIe5 may be a good solution.

The shared prices above just prove that there is no future for the PCIe 5 standard because it will make the boards prohibitively expensive, which is not what we need.

We need PCIe 4 for now and the next several years.

Most people still have access to primitive 500 MB/s read/write SSDs, so even PCIe 4 is a giant step forwards.

That's not how it works though.
For one, PCB's don't have wires, they have multiple layers with copper traces, but you can't simply make those traces thicker or wider, it's not enough to improve the signal. For PCIe 5.0 we're talking transfer rates of 32 Gigatransfers per second, so any kind of interference is going to mess that up.
Yes, the board makers shifted to more advanced PCB materials with PCIe 4.0, but this isn't directly related to the copper traces, but rather to the material the PCB is made from, to try and reduce interference and noise.
Keep in mind that one retimer isn't going to be enough if you want all slots on a motherboard to be PCIe 5.0, you're most likely going to need a couple of them, so that's $50 or more on the retail price of a motherboard for something that's unlikely to benefit any consumer for at least the next five years.
The average ATX size X570 board seem to use three to five redrivers, depending on the design. That alone is $12 or more, which I'm expecting will still be required in combination with the retimers.

But the redrivers/retimers costs don't directly go in the final retail price for the consumer - they still get a very significant profit margin on top.

 

[Valantar]

I guess we all did read that Intel's first PCIe 5 implementation for consumers is incomplete at best, but the fact remains. PCIe 4 came way too late and after 2023 it will mostly survive as the budget option. Let's not forget e.g. that last year PCIe 4 GPUs helped AMD to beat Intel in gaming performance and that next-gen flagship GPUs are rumored to be 2-2,5 times more powerful.

Wait, what? There is no perceptible performance difference between PCIe 3.0 x16 and 4.0 x16 for current-gen GPUs. The lack of PCIe 4.0 was not what held Intel back whatsoever, it was AMD's faster core design that helped them get ahead.

Also, PCIe bandwidth demands don't scale linearly with GPU power. Not even close. A 2-2.5x increase in render performance does not mean a 2-2.5x increase in bandwidth demands. Most likely bandwidth demands will increase by a relatively small percentage, as they have been doing with each generation for a decade. There's zero indication that this will suddenly become a major bottleneck. The 2080 Ti was the first GPU where there was a notable (>1%) difference between PCIe 3.0 x16 and x8. And that of course doesn't mean that it needed the full bandwidth of x16, just that x8 was slightly less than optimal - 9 or 10 lanes might have been completely sufficient. PCIe 4.0 x16 has doubled what was already sufficient, in other words there is still tons of headroom, and there is <1% difference in performance for the current fastest GPUs between 3.0 and 4.0 x16. There's no reason for 4.0 to remain a budget option, as it will in all likelihood provide 100% of the performance of any PCIe 5.0 GPU launched in the next five years (if not longer). All the while it will have cheaper motherboards.

PCIe 4.0 was indeed late, but not in a way that mattered to end users in any way whatsoever. It held datacenters back, but the rest of us? Nope. And 4.0 is still plenty for us, and will be for the next 5+ years in all but the most extreme cases.

 

[Selaya]

[ ... ]The lack of PCIe 4.0 was not what held Intel back whatsoever, it was AMD's faster core design that helped them get ahead.

[ ... ]

Nitpicking, but what made Vermeer beat Skylake at long last is primarily and pretty much exclusively due to the colossal 32MiB of L3 (Skylake maxes out at 20 for the 10900(K)/10850).

 

[docnorth]

That's not how it works though.
For one, PCB's don't have wires, they have multiple layers with copper traces, but you can't simply make those traces thicker or wider, it's not enough to improve the signal. For PCIe 5.0 we're talking transfer rates of ~4GB/sec, per direction, per lane, so any kind of interference is going to mess that up.
Yes, the board makers shifted to more advanced PCB materials with PCIe 4.0, but this isn't directly related to the copper traces, but rather to the material the PCB is made from, to try and reduce interference and noise.
Keep in mind that one retimer isn't going to be enough if you want all slots on a motherboard to be PCIe 5.0, you're most likely going to need a couple of them, so that's $50 or more on the retail price of a motherboard for something that's unlikely to benefit any consumer for at least the next five years.
The average ATX size X570 board seem to use three to five redrivers, depending on the design. That alone is $12 or more, which I'm expecting will still be required in combination with the retimers.
The redrivers have improved since the X570 chipset launched, as it seems early redrivers could only handle two PCIe lanes, whereas more recent ones seems to be able to handle up to four PCIe lanes, so that might allow for some cost savings.

Some interesting bits here as well, which shows the difference between a redriver and a retimer.

PCI Express® Retimers vs. Redrivers: An Eye-Popping Difference | PCI-SIG

pcisig.com

Love engineering groups that don't use metric...
Anyhow, this shows that moving from PCIe 4.0 to 5.0 cuts about 40% of the trance length due to signal loss.
Right now, high-end motherboards are using low-loss PCBs.
Keep in mind that this is trace length, which is much longer than the distance of the slot from the chipset/CPU.

View attachment 213604

Retimers to the Rescue Webinar: PCI-SIG® Q&A | PCI-SIG

pcisig.com

Actually a PCIe 4 board should have less redrivers than a PCIe 3 board, because for PCIe 4 speeds they are replaced by (more expensive) retimers. But if the additional cost of the retimers is indeed more than 50-60 eur/usd for a quality motherboard (which I don’t believe will be the case), @TumbleGeorge has a point, manufacturers should start considering different and for now very expensive PCB materials for mass production.

 

[Valantar]

Nitpicking, but what made Vermeer beat Skylake at long last is primarily and pretty much exclusively due to the colossal 32MiB of L3 (Skylake maxes out at 20 for the 10900(K)/10850).

Well, in this regard cache allocation is very much part of the core design - at least to the extent that you can't speak of any kind of performance or IPC metric without including the cache. Technically it's separate, and mobile/APU Zen 3 does have a different cache layout - and thus slightly different IPC - but that's also fundamentally different in other significant ways (monolithic vs. chiplets, etc.). So, yeah, technically correct, but also not in practice. One could of course also speak of the effects of the cache layout, associativity, latencies, etc., etc. There are always more details to point out

Actually a PCIe 4 board should have less redrivers than a PCIe 3 board, because for PCIe 4 speeds they are replaced by (more expensive) retimers. But if the additional cost of the retimers is indeed more than 50-60 eur/usd for a quality motherboard (which I don’t believe will be the case), @TumbleGeorge has a point, manufacturers should start considering different and for now very expensive PCB materials for mass production.

Did you mean 5 and 4? And part of what @TheLostSwede said was that 5.0 boards might ened redrivers in addition to retimers, and not just instead of. There's also a question of whether more mass market adoption will drive down proces for "for now very expensive PCB materials". Material costs don't generally tend to drop if demand increases, and unless production techniques here scale very well, there won't be any real volume scaling either. There are few expectations of lower interference motherboards and materials dropping noticeably in price. Which means that we instead get more expensive products.

Heck, it's the same with cables - just because USB-C cables are now ubiquitous doesn't mean that they're the same price as old USB 2.0 micro-B cables. They never will be, as there are more materials, more complex production techniques, and both are at commodity volumes already. (You might find USB 2.0-only, low amperage usb-C cables at close to the same costs as USB 2.0 micro-B cables, but it's not going to hit parity, ever.)