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Yields of Intel Sapphire Rapids Processors Are Low, Mass Production to Start in 1H2023

AleksandarK

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Intel's upcoming Sapphire Rapids processors have faced multiple delays over the past few years. Built on Intel 7 manufacturing process, the CPU is supposed to bring new advances for Intel's clients and significant performance uplifts. However, TrendForce reports that the mass production of Sapphire Rapids processors will be delayed from Q4 of 2022 to the first half of 2023. The reason for this (yet another) delay is that the Sapphire Rapids MCC die is facing a meager yield on Intel 7 manufacturing technology, estimated to be at only 50-60% at the time of writing. Economically, this die-yielding percentage is not profitable for Intel since many dies are turning out to be defective.

This move will stop many OEMs and cloud service providers (CSPs) from rolling out products based on the Sapphire Rapids design and will have to delay it until next year's mass production. On the contrary, AMD is likely to reap the benefits of Intel's delay, and AMD's x86 server market share will jump from 15% in 2022 to 23% in 2023. Given that AMD ships processors with the highest core counts, many companies will opt for AMD's solutions in their data centers. With more companies being concerned by their TCO measures with rising energy costs, favors fall in the hand of single-socket servers.




The source also cites that Intel has supply issues with low-end FPGA devices made by its Altera division that affect shipments of dual-socket systems. As a replacement, these dual-socket systems use Lattice CPLDs, which are also in low supply. This is why many CSPs and OEMs are now turning their heads to AMD and its solutions that are simpler to operate and have lower TCO. TrendForce thus predicts that AMD CPUs will reach a 25% market share in Q4 of 2023, with an annual growth rate of 7%.

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at this point it's more a feature then a bug
 
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moar liek Sapphire Rapidly losing interest amIright?!?
 
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This period of time we read
- bad news for AMD in the retail market (AM5 sales)
- bad news for Intel in the server market (SP)

At least there is a balance this way.
 
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So, Intel still having issues with their ancient 10nm process? wow!
 
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What about Ponte Vecchio? This computing unit is also super delayed and there hasn’t been a whisper about it in awhile.
 
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This period of time we read
- bad news for AMD in the retail market (AM5 sales)
- bad news for Intel in the server market (SP)

At least there is a balance this way.
For AMD they can just shift more CCDs towards EPYC.
For Intel their Xeons and Desktop chips are different dies so it is more of an issue.
 
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AMD is about to release Zen 4 Epyc at 96 cores on Nov 10, 2022 with presumably Zen 4 Epyc-X with 3d v-cache on the way. As long as SPR is delayed, Intel’s best enterprise CPU is the 40 core dual socket Ice Lake based Xeon. I don’t see SPR catching up even with HBM.
 
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That's surprisingly awful even with their track record. I don't even want to consider what the yields would be with a monolithic die.
 
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So, Intel still having issues with their ancient 10nm process? wow!
It's more like, "Wow, chiplets are actually way harder than Intel fanboys gave AMD credit for." The real question is, if Intel is having trouble with four identical tiles on one CPU, how are they going to successfully produce something like Meteor Lake that has four different tiles made on three different manufacturing processes?
 
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It's more like, "Wow, chiplets are actually way harder than Intel fanboys gave AMD credit for." The real question is, if Intel is having trouble with four identical tiles on one CPU, how are they going to successfully produce something like Meteor Lake that has four different tiles made on three different manufacturing processes?
... by three manufacturers on two continents, and with three supply chains over all continents. Hm, is the Suez canal better managed now than it was in March of 2021?

meager yield on Intel 7 manufacturing technology, estimated to be at only 50-60%
This needs some context. Is this the % of chips with all cores good, or % of chips with uncore logic OK and enough functional cores for Intel to not be ashamed of selling them?
 
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AMD with the ZEN4 EPYCs and YET Another server socket cause why not.
This time with more wafers available for server due to the crap launch of the AM5 desktops...
lets wait and see the reviews on the 96cores zen4 epyc and 3DV Cache stuff.
 
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Reposting this until Sapphire Rapids releases, week 70-something.

1667316819391.png

 
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Reposting this until Sapphire Rapids releases, week 70-something.

View attachment 268126

I remember reading review of Icelake on anandtech and it was a disappointing "upgrade" at best.
 
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I remember reading review of Icelake on anandtech and it was a disappointing "upgrade" at best.
Lot of people here concentrate on the laptop and desktop side and say how much Intel is winning. But the fact of the matter is that Intel is tied with AMD at best in the minds of mainstream users in these two markets. But when it comes to enterprise, Intel is in extreme trouble. A two year delay with big data customers is like a death knell.
 
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Oh shit, this is SERIOUS.

Sapphire Rapids is the first product using Intels Foveros "tile-based chiplets"

The point of this is to make smaller, easier-to-manufacture tiles, rather than big monolithic dies - because yields on smaller tiles are always going to be higher than on big monolithic dies.

Maybe I'm missing something here, but if yields are only 50-60% on small tiles, Intel's foundry execution is even worse than I thought, and I was already pretty cynical.

Sapphire Rapids largest tile is apparently 400mm^2. That's in the same ballpark as Navi22 (RX 6700XT) on TSMC N7 and GA104 (3070) on Samsung 8, so it's not as if yields should be that low....
 
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Oh shit, this is SERIOUS.

Sapphire Rapids is the first product using Intels Foveros "tile-based chiplets"

The point of this is to make smaller, easier-to-manufacture tiles, rather than big monolithic dies - because yields on smaller tiles are always going to be higher than on big monolithic dies.

Maybe I'm missing something here, but if yields are only 50-60% on small tiles, Intel's foundry execution is even worse than I thought, and I was already pretty cynical.

Sapphire Rapids largest tile is apparently 400mm^2. That's in the same ballpark as Navi22 (RX 6700XT) on TSMC N7 and GA104 (3070) on Samsung 8, so it's not as if yields should be that low....

Well Tiles based Sapphire rapids is a more advanced packaging than AMD EPYC. It's really mean to have 4 chips that act like a single one where EPYC is to have multiples chips that work together with an I/O die.

So it's much more difficult to achieve and that reflect so much all the problem Intel have and why they struggle those days versus AMD and TSMC.

The philosophy of AMD and TSMC is to do small incremental improvement to the technology that are manageable and that can be delivered on time. They take smaller chunk, but they manage to deliver them.

Intel on the other hand, want to do big audacious and drastic change. They always optimistic about delivering them but in the end, they always face huge challenge that they take years to overcome and deliver their product late.

This is what happened to their foundry business and this is what happening with their Datacenter cpus. (We can also add ponte veccio).

Those big leaps were possible in the past and Intel did many of them. But these days, things are so complex and expensive that it's a suicidal strategy. They need to step back and take bites they can handle and they will start succeeding again. Else, those big leaps might lead them to bankruptcy if they continue to be uncompetitive in many markets.
 
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Reposting this until Sapphire Rapids releases, week 70-something.
Do you mean that they will release it in 70th week of this year, with the date code 2270?
 
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Well Tiles based Sapphire rapids is a more advanced packaging than AMD EPYC. It's really mean to have 4 chips that act like a single one where EPYC is to have multiples chips that work together with an I/O die.
I understood this news article as "the individial tile yields are only 50-60%" which has nothing to do with the packaging.

If the reality is that Foveros packaging itself is ruining perfectly good tiles, then Intel have an even bigger problem, because tile-based Foveros is their entire roadmap going forward. If that doesn't work, they have nothing to sell beyond what's already in the market right now!
 
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Well Tiles based Sapphire rapids is a more advanced packaging than AMD EPYC. It's really mean to have 4 chips that act like a single one where EPYC is to have multiples chips that work together with an I/O die.

So it's much more difficult to achieve and that reflect so much all the problem Intel have and why they struggle those days versus AMD and TSMC.
The basic idea is great, even revolutionary. Stitching the mesh buses into one with minimum or no interface logic, which is inevitably slow and eats a lot of power. The execution however ... yeah, as you said.
 
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