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AVX-512 is not an instruction, it is an instruction set extension. This does not directly affect the core x86-64.Can you explain the failure of this instruction: AVX-512? It turned out to be a power hog, and was abandoned.
Why was that? And what solution does RISC-V have to compute as an alternative?
It is a power hog mainly because it deals with 512-bit operands. Longer registers, wider execution units. There are good use cases for AVX-512, the hardware implementation just was not there and the question became whether it is worth it. For these instructions to work the hardware implementation can be different. AMD started supporting AVX-512 in Zen4 by using two 256-bit floating pipes together and only in Zen5 by extending the length of floating point units.
What do you mean what solution does RISC-V have to compute as an alternative?
AVX-512 does not come from empty space. There was MMX, then there were versions of SSE and 3DNow!, then AVX, AVX2 and now AVX-512. Width of operations increased along with that as well. Aside from operations themselves also the amount of data being processed. IIRC SSE brought 128-bit, AVX2 256-bit (and heat issues in Haswell and Skylake), AVX-512 brought 512-bit. There are use cases - mostly related to multimedia - where SIMD and wider data processing is beneficial.
ARM isn't different either. There were SIMD, VFP (not SIMD but vector), Advanced SIMD/NEON extensions at one time or another. These are the successful ones that survived (or a version for them did). And these were not a standard functionality in ARM until some point (v8?). This type of operations are now being added to ARM proper (at a somewhat slower pace).
RISC-V will have to basically walk the same path once it starts to work with the same or similar data or algorithms. Wider operations, bigger units. At some point they cannot affort to keep on doing things by 64-bit chunks when competition does 2, 4 or 8 times wider (for example see what AMD did with AVX2 and AVX-512 support - initially made do with smaller units and used 2 of them to do the operation but then made the units bigger in the next iteration). Whether that will end up with more complex operations is an interesting topic and we will have to see. In theory they can keep the hardware simple but that will only move the same complexity to software.