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AMD Launches Ryzen 9 9000X3D Series "Zen 5" Desktop Processors with 3D V-Cache

bug

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Dual V-cache = extra cost for very little gaming performance improvement. You want the games pinned to one CCD anyway, as soon as it jumps CCD you get a performance loss whether the other CCD has V-cache or not. The ideal scenario is to pin the games to the V-cache CCD. When that happens. what will the other CCD with V-cache do with all that extra cache sitting in the there if both CCD's have V-cache?

Having V-cache on one CCD is ideal. If you want V-cache on the other CCD as well to minimize performance loss for games that jump CCD, which is literally the only reason one might want it, just use project lasso for that specific game. Now why would I want dual CCD to increase performance for those specific games when I can get higher performance with a single (or dual) V-cache CPU by just pinning it to the correct CCD with lasso. Once pinned, there is going to be zero difference between dual and single CCD V-cache.

In my 7950X3D I only noticed older games jumping CCD and among the 20 or so games I tested it was only the one game that regressed performance slightly.

Edit: If AMD completely overhauls the design and other CCD's cache can be shared without going through the IF, maybe dual CCD cache might make sense. At present, it's pretty pointless
 
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A cpu is not only for gaming.

I want a processor which is the same. Nothing half baked. It makes my task optimising the code for the hardware impossible.

The ideal scenario is to pin the games to the V-cache CCD.

No. No. No.

The ideal scenario is a symmetrical processor. So you do not need any software overhead to manage those tasks. Maybe my ryzen 7600x is symmetrical.

E-Cores = overhead
cache tile vs no cache tile = performance penalty // software overhead by pinning software to the V-Cache CCD. - moving software to the desired cores.
 
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Core parking should be working correctly for dual CCD CPUs for months now.

This is how it’s supposed to be on 7000X3D when the nonV-cached CCD has much higher frequency.

Here the game is loading and the threads are handled mostly on nonV-cached CCD

IMG_8529.jpeg

Here the loading ended and 3D graphics are on handled (switched) at the V-cached CCD while the higher frequency is handling background threads.

IMG_8530.jpeg

Nothing is disabled ever. Just proper scheduling.
Dual CCD 7000X3Ds are suppose to run a dedicated win service for this.

IMG_8531.jpeg

 

bug

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A cpu is not only for gaming.

I want a processor which is the same. Nothing half baked. It makes my task optimising the code for the hardware impossible.
Then get anything other than an X3D CPU.
X3D is not "half-baked". It's built to dominate gaming benchmarks first and foremost. It does that rather well.
 
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Its unusual to see half-baked products to be ahead of the full baked ones...

1736298535920.png
 
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A cpu is not only for gaming.

I want a processor which is the same. Nothing half baked. It makes my task optimising the code for the hardware impossible.



No. No. No.

The ideal scenario is a symmetrical processor. So you do not need any software overhead to manage those tasks. Maybe my ryzen 7600x is symmetrical.

E-Cores = overhead
cache tile vs no cache tile = performance penalty // software overhead by pinning software to the V-Cache CCD. - moving software to the desired cores.
I meant ideal in the 9950x3d's current state with either single or dual ccd v-cache. What you're saying is the ideal scenario in general, with which i agree.
 
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Then get anything other than an X3D CPU.

OMG

Just for information: Other tasks benefit also from cache.

I will not explain what purpose an arithmetic logic unit, cache and a scheduler has.

Just use a very old windows version without those "software" fixes for those "unbaked" processors. We had those topics for months in the past. Denying facts?
 

bug

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OMG

Just for information: Other tasks benefit also from cache.
Well then. Don't buy anything, I guess?
I will not explain what purpose an arithmetic logic unit, cache and a scheduler has.

Just use a very old windows version without those "software" fixes for those "unbaked" processors. We had those topics for months in the past. Denying facts?
This doesn't make sense, I'll pretend you didn't post these.
 
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I want a processor which is the same. Nothing half baked. It makes my task optimising the code for the hardware impossible.
Cache-aware designs are a thing. Scheduling hints for heterogeneous CPUs (both E/P cores, and also CPUs with more cache or frequency) are available in linux as well, so you can make use of that.
The ideal scenario is a symmetrical processor. So you do not need any software overhead to manage those tasks. Maybe my ryzen 7600x is symmetrical.
Your 7600x is not symmetrical from a high performance optimization perspective, since you need to be aware of when you're running a CPU in 1T or 2T mode, and being aware of when to use sibling threads in a single core or try to leave CPUs solely in 1T mode to not compete for resources.
Extra E-cores, or cache vs frequency cores is just adding nuances to the above, but it's still the same idea.
Just for information: Other tasks benefit also from cache.
Eh, not many that you would want to run in a puny consumer CPU with only a 128-bit memory bus. Apart from games, it's often CFD and Database stuff that's really sensitive to bandwidth, which cache helps a lot, but that you should be using more memory channels to begin with.
I will not explain what purpose an arithmetic logic unit, cache and a scheduler has.
I don't think this has anything to do with the discussion and you seen to be trying to move the goalposts.
 
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Why AMD!? Why only one CCD with 3D cache?
Incidentally, AMD has recently addressed this question. I speculated on a recent article (one that confirmed the upcoming Ryzen 9 X3Ds would again be single-CCD-with-cache affairs) that perhaps it's not because of a technical barrier but rather it's possibly a business choice because the costs probably far outweigh the performance benefits. The reason AMD gave was... exactly that.

Cache on both CCDs won't help in most games since few, if any, games meaningfully use more than eight cores (at least to the extent to see a real benefit), and for those few that might, crossing CCDs has performance penalties that largely counteracts (if not more than negates?) the benefit. So you would be left with a processor that now needs to be much more expensive for very very little benefit, if any at all. At least for most things/gaming. I mean, maybe it's a cool concept to speculate about for something like Minecraft with Distant Horizons (which scales with core count and I don't think latency matters much, and that's presuming the LOD generation is even sped up by extra cache which I'm not sure of so maybe the current hybrid approach works just as well) or something, but... yeah, those types of niches are too uncommon to make it worthwhile for now.

What about the non-gaming situations where it could benefit massively? There's always exceptions, but it seems they are too few in number (at least for now, and at least in AMD's opinion) to make it worthwhile. Making the CPU that way would mean it needs to be even more expensive, meaning they will likely lose more buyers than they gain in profits from those abstaining from buying it over this single fact.

So "it's not worth the additional cost/resulting higher price we'd need to charge because the benefits are too few/low". This isn't just my speculation anymore; it's the very reason AMD has recently claimed as to why they aren't doing it.
 
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Incidentally, AMD has recently addressed this question. I speculated on a recent article (one that confirmed the upcoming Ryzen 9 X3Ds would again be single-CCD-with-cache affairs) that perhaps it's not because of a technical barrier but rather it's possibly a business choice because the costs probably far outweigh the performance benefits. The reason AMD gave was... exactly that.

Cache on both CCDs won't help in most games since few, if any, games meaningfully use more than eight cores (at least to the extent to see a real benefit), and for those few that might, crossing CCDs has performance penalties that largely counteracts (if not more than negates?) the benefit. So you would be left with a processor that now needs to be much more expensive for very very little benefit, if any at all. At least for most things/gaming. I mean, maybe it's a cool concept to speculate about for something like Minecraft with Distant Horizons (which scales with core count and I don't think latency matters much, and that's presuming the LOD generation is even sped up by extra cache which I'm not sure of so maybe the current hybrid approach works just as well) or something, but... yeah, those types of niches are too uncommon to make it worthwhile for now.

What about the non-gaming situations where it could benefit massively? There's always exceptions, but it seems they are too few in number (at least for now, and at least in AMD's opinion) to make it worthwhile. Making the CPU that way would mean it needs to be even more expensive, meaning they will likely lose more buyers than they gain in profits from those abstaining from buying it over this single fact.

So "it's not worth the additional cost/resulting higher price we'd need to charge because the benefits are too few/low". This isn't just my speculation anymore; it's the very reason AMD has recently claimed as to why they aren't doing it.
To add to your point, so far it has been said that AMD won't even make a Turin-X version, meaning that Genoa-X will be the current Epyc V-cache offering still. I guess for the CFD/HPC stuff those often get deployed, the AVX512 benefits are not meaningful enough over the IO-bound aspect to justify a new lineup.
So yeah, the extra cache is really only meaningful for some niche workloads even in the enterprise space.
 
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To add to your point, so far it has been said that AMD won't even make a Turin-X version, meaning that Genoa-X will be the current Epyc V-cache offering still. I guess for the CFD/HPC stuff those often get deployed, the AVX512 benefits are not meaningful enough over the IO-bound aspect to justify a new lineup.
So yeah, the extra cache is really only meaningful for some niche workloads even in the enterprise space.

I don't remember who mentioned it, but might have been Ian Cuttress in one of his podcasts. The reason AMD didn't release Turin-X is not so much about the market being niche (it is, compared to the elephant(s) in the room) but because the clients using V-Cache CPU's typically upgrades every two generations. So they assessed the market and realized Genoa-X will tide them over just fine till Zen 6 V-Cache, so expect to see a ton of 10 core V-cache Zen 6 CCD's in the future.

I made the last part up but one can hope.
 
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