AMD Launches Ryzen 9 9000X3D Series "Zen 5" Desktop Processors with 3D V-Cache

[JoeTheDestroyer]

Is it? We know this for sure? Or just with older dual CCD X3D models?

It was never true. Core parking is not the same as disabled, It's basically just a stronger hint to avoid scheduling on those cores, Windows can and does violate it.

 

[igormp]

It says so in the article, its coming from the presentation :"and AMD has worked to refine its software-based OS scheduler optimization such that productivity applications favor either of the CCDs, while games stick to the one with 3D V-Cache."

It's not "disabled", other background stuff can still run in the non-x3D CCD, but games get "pinned" to the X3D CCD. Similar to how you can pin a process to some specific cores with something like process lasso.

Oh..

View attachment 378644

Now load up more cores and see the clocks falling

 

[Shakallia]

Oh..

View attachment 378644

You can get that kind of result with any processor if you lucky on the silicon lottery, because it always comes to that, may you buy a 9600x, 9700x, 9900x or 9950x etc..

It's not "disabled", other background stuff can still run in the non-x3D CCD, but games get "pinned" to the X3D CCD. Similar to how you can pin a process to some specific cores with something like process lasso.

Now load up more cores and see the clocks falling

Yes, I was only speaking for gaming. Its disabled for gaming, that's how I meant it. If you read my first post, I was explicitly talking about gaming scenarios.

I'm quoting myself here :" In gaming, the other ccd is disabled"

 

[igormp]

You can get that kind of result with any processor if you lucky on the silicon lottery, because it always comes to that, may you buy a 9600x, 9700x, 9900x or 9950x etc..


Yes, I was only speaking for gaming. Its disabled for gaming, that's how I meant it. If you read my first post, I was explicitly talking about gaming scenarios.

I'm quoting myself here :" In gaming, the other ccd is disabled"

I got what you meant, it's just a semantics issue. Disabled implies it doesn't work/can't be used, which is not the case.
If a game for some reason requires more cores, even with this scheduler prioritization it could spill into the 2nd CCD given the x3D ones becomes too busy.

 

[Guwapo77]

This is going to be the best gaming chip on the planet. Same frequency as the non X3D part, its going to be magical. As soon as its available for purchase, its bought!

 

[Crackong]

Disappointed to see no dual CCD dual X3D part tho.

 

[Bagerklestyne]

Now more than ever I want to see a frequency locked 7800X3D and 9800X3D (say 4 to 4.5ghz) so we can see how much was generational ipc and how much simply boost clock.

 

[Shakallia]

I got what you meant, it's just a semantics issue. Disabled implies it doesn't work/can't be used, which is not the case.
If a game for some reason requires more cores, even with this scheduler prioritization it could spill into the 2nd CCD given the x3D ones becomes too busy.

I'm not convinced at all, especially given the fact that core parking is a way to avoid latency issue between the 2 ccd's, so I believe that by tweaking it (the scheduler), they kind of imply enforcing the fact that the games only uses the x3d ccd cores.

 

[mkppo]

Meh, i'll still get it in the hope of getting luckier than my 9950X and it's garbo IMC. Should pair up nicely with the Apex. Atleast now there's no productivity penalty compared to 9950X.

 

[bug]

You clearly do not understand that only ONE ccd has 3dv cache. In gaming, the other ccd is disabled, so you're basically comparing two 8 core 3dvcache processors, one with higher boost clock and lower base frequency, and one with higher base frequency abd lower boost clock.

The cores are still there. They will be used if the others are under load. The 3DVCache cores will be preferred, that's all.

 

[trparky]

Why AMD!? Why only one CCD with 3D cache?

 

[Aken Bosch]

Why AMD!? Why only one CCD with 3D cache?

Cost and diminishing returns (more likely). The generation that will launch along with the new consoles I'm sure they will though (call it a hunch).

 

[trparky]

Cost and diminishing returns (more likely). The generation that will launch along with the new consoles I'm sure they will though (call it a hunch).

But why not have an option to buy dual 3D cache models?

 

[Aken Bosch]

Desktop CPU's. You'll get dangerously close to server territory, where the margins are higher. Why would you kill a gold goose?

 

[bug]

Why AMD!? Why only one CCD with 3D cache?

The answer is right there: Core Complex Die. You cannot have on-die cache across two dies. You could have two different caches, but they will not help much, since the data wouldn't be coherent.

 

[trparky]

The answer is right there: Core Complex Die. You cannot have on-die cache across two dies. You could have two different caches, but they will not help much, since the data wouldn't be coherent.

But the L3 cache on non-3D cache chips aren't coherent either. What's the difference between a CCD with 3D cache and one without? Not much from what I can see other than that 3D cache gives a whole lot more L3 cache.

 

[bug]

But the L3 cache on non-3D cache chips aren't coherent either. What's the difference between a CCD with 3D cache and one without? Not much from what I can see other than that 3D cache gives a whole lot more L3 cache.

Bingo!

 

[trparky]

So why not have two CCDs as versus one CCD that have shit loads of L3 cache?

 

[bug]

So why not have two CCDs as versus one CCD that have shit loads of L3 cache?

That's chiplet design for you. Chiplets are only as big as you can make without too many defects.

 

[trparky]

That's chiplet design for you. Chiplets are only as big as you can make without too many defects.

But correct me if I'm wrong but don't all CCDs, even the 3D cache CCDs, start off as plain CCDs and the 3D cache is just bolted to it?

 

[bug]

But correct me if I'm wrong but don't all CCDs, even the 3D cache CCDs, start off as plain CCDs and the 3D cache is just bolted to it?

I couldn't tell how they're made otoh. But even if they were made the way you describe, you have yields for the CCD, yields for the cache and then yields for the finished product (because simply combining them together can break some).

Regardless, even if both CCDs would have 3DCache added, migrating threads would need their data pulled again from RAM which I suspect negates the advantage of 3DVCache. Probably the numbers (which only AMD has) indicated you win more benchmarks if you put a bigger cache on one CCD than if you put a smaller cache on both CCDs.

 

[trparky]

I couldn't tell how they're made otoh. But even if they were made the way you describe, you have yields for the CCD, yields for the cache and then yields for the finished product (because simply combining them together can break some).

I didn't think about that.

Regardless, even if both CCDs would have 3DCache added, migrating threads would need their data pulled again from RAM which I suspect negates the advantage of 3DVCache.

Another thing I didn't think about. Yeah, that makes sense.

I guess I was just caught up in the idea of more cache, more better.

 

[bug]

I guess I was just caught up in the idea of more cache, more better.

There's this knee-jerk reaction that you see on the Internet, that companies have their engineers neuter their products for various reason (depending on what you read, someone will have that opinion about any company). That leaves an impression and can add some thought-bias. And while I am sure in some cases that is true, what usually happens is engineers will come up with something on the drawing board and that something gets adjusted because a) real world testing and b) production/supply realities.

In particular "the more cache, the better" was never true. Because the more cache, the higher the latency. Correctly sizing a cache for an architecture is so complicated that, as you can see, landed us with 4 levels of cache, each still able to put more performance on the table. Without the latency problem, we'd have one huge 1st level cache (kidding, that's not possible, for different reasons).

 

[igormp]

I couldn't tell how they're made otoh. But even if they were made the way you describe, you have yields for the CCD, yields for the cache and then yields for the finished product (because simply combining them together can break some).

AFAIK the V-cache is made on a cheaper node (expected since it's both cheaper and SRAM has shitty size scaling anyway).

 

[trparky]

Because the more cache, the higher the latency.

Why is that?