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| System Name | RBMK-1000 |
|---|---|
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| Power Supply | Cooler Master MWE Gold 650W |
| Mouse | ASUS ROG Strix Impact |
| Keyboard | Gamdias Hermes E2 |
| Software | Windows 11 Pro |
AMD is readying two important client segment processors powered by the next-generation "Zen 6" microarchitecture, according to a sensational new report by Moore's Law is Dead. These are the "Medusa Point" mobile processor, and the "Olympic Ridge" desktop. The former is a BGA roughly the size and Z-Height of the current "Strix Point," but the latter is being designed for the existing Socket AM5, making it the third (and probably final) microarchitecture to do so. If you recall, Socket AM4 served three generations of Zen, not counting the refreshed "Zen+." At the heart of the effort is a new CPU complex die (CCD) that AMD plans to use across its client and server lineup.
The "Zen 6" performance CCD is being designed for a 3 nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.
Going all the way back to the Ryzen 3000 series "Matisse," the two CCDs on the client desktop processor have had Infinity Fabric links to the I/O die, but no direct high-bandwidth interconnects between the two CCDs. For threads to migrate between cores of the two CCDs, they would have to make a round-trip through the main memory. AMD is looking to solve this with the introduction of a new low-latency bridge connection between the two CCDs. If the goal is to enable threads to seamlessly migrate among cores of the two CCDs, cutting out round-trips to the main memory, then the purpose of this bridge interconnect is to establish cache coherency between the two CCDs. This would vastly lower intercore latency.
Here's where things get very interesting. Apparently, the "Medusa Point" mobile processor is chiplet-based, and will use a single 12-core "Zen 6" chiplet, with a large mobile client I/O die built on an older node, likely the N4P. This mobile cIOD will contain an updated iGPU that's powered by the newer RDNA 4 graphics architecture. It will also contain the chip's memory controllers, and an updated NPU. We hope AMD works to increase the number of PCIe lanes put out by this I/O die, or at least update it to PCIe Gen 5. Pictures show small rectangular structures on the mobile client I/O die causing some speculation that it is some kind of low power island CCX with "Zen 6c" cores, although MLID lays this to rest by saying that these are workgroup processors (WGPs) of the iGPU. There are eight of these and a large slab of L2 cache, which seems to confirm that the iGPU is based on the RDNA 4 graphics architecture, and has 16 compute units (CU).
Since AMD is using the same CCD for "Medusa Point" as the "Olympic Ridge" desktop processor, you could expect variants of "Medusa Point" with 3D V-Cache. The 3D V-Cache technology is expected to be implemented on "Zen 6" much in the same way it is on "Zen 5," with an upside-down stacking—3D V-Cache die (L3D) below, with CCD on top.
Given the increase in CPU core counts, especially with "Olympic Ridge" getting up to 24 cores with two CCDs, and the inter-CCD bridge interconnect for cache coherency, AMD is going to need a new client I/O die for desktop. We've already discussed this in older articles. The new cIOD is expected to be built on the Samsung 4LPP (4 nm EUV) foundry node, which offers improvements over the TSMC N6 DUV node the current cIOD is being built on. A key area of focus for AMD will be the memory controllers, which will be updated to support higher DDR5 memory speeds using technologies such as CKD. You can currently run a "Granite Ridge" processor with memory speeds of up to DDR5-8000 but using a 1:2 clock divider is engaged between FCLK and MCLK, with 1:1 speeds being limited to around DDR5-6400. The new memory controllers will look to increase speeds with 1:1, and unlock speeds beyond 10000 MT/s with 1:2.
Then there's the matter of AI acceleration, and the new cIOD will present AMD with the opportunity to implement at least a 50 TOPS-class XDNA 2 NPU. Intel received flack for giving its "Arrow Lake" processors a 16 TOPS-class NPU that doesn't meet Copilot+ requirements, and the company is probably working to fix this in "Panther Lake," and so if AMD decides to implement an NPU on the cIOD for "Olympic Ridge," we predict it will be at least 50 TOPS-class.
View at TechPowerUp Main Site | Source
The "Zen 6" performance CCD is being designed for a 3 nm-class node, likely the TSMC N3E. This node promises a significant increase in transistor density, power, and clock speed improvements over the current TSMC N4P node being used to build the "Zen 5" CCD. Here's where it gets interesting. The CCD contains twelve full-sized "Zen 6" cores, marking the first increase in core-counts of AMD's performance cores since its very first "Zen" CCD. All 12 of these cores are part of a single CPU core complex (CCX), and share a common L3 cache. There could be a proportionate increase in cache size to 48 MB. AMD is also expected to improve the way the CCDs communicate with the I/O die and among each other.
Going all the way back to the Ryzen 3000 series "Matisse," the two CCDs on the client desktop processor have had Infinity Fabric links to the I/O die, but no direct high-bandwidth interconnects between the two CCDs. For threads to migrate between cores of the two CCDs, they would have to make a round-trip through the main memory. AMD is looking to solve this with the introduction of a new low-latency bridge connection between the two CCDs. If the goal is to enable threads to seamlessly migrate among cores of the two CCDs, cutting out round-trips to the main memory, then the purpose of this bridge interconnect is to establish cache coherency between the two CCDs. This would vastly lower intercore latency.
Here's where things get very interesting. Apparently, the "Medusa Point" mobile processor is chiplet-based, and will use a single 12-core "Zen 6" chiplet, with a large mobile client I/O die built on an older node, likely the N4P. This mobile cIOD will contain an updated iGPU that's powered by the newer RDNA 4 graphics architecture. It will also contain the chip's memory controllers, and an updated NPU. We hope AMD works to increase the number of PCIe lanes put out by this I/O die, or at least update it to PCIe Gen 5. Pictures show small rectangular structures on the mobile client I/O die causing some speculation that it is some kind of low power island CCX with "Zen 6c" cores, although MLID lays this to rest by saying that these are workgroup processors (WGPs) of the iGPU. There are eight of these and a large slab of L2 cache, which seems to confirm that the iGPU is based on the RDNA 4 graphics architecture, and has 16 compute units (CU).
Since AMD is using the same CCD for "Medusa Point" as the "Olympic Ridge" desktop processor, you could expect variants of "Medusa Point" with 3D V-Cache. The 3D V-Cache technology is expected to be implemented on "Zen 6" much in the same way it is on "Zen 5," with an upside-down stacking—3D V-Cache die (L3D) below, with CCD on top.
Given the increase in CPU core counts, especially with "Olympic Ridge" getting up to 24 cores with two CCDs, and the inter-CCD bridge interconnect for cache coherency, AMD is going to need a new client I/O die for desktop. We've already discussed this in older articles. The new cIOD is expected to be built on the Samsung 4LPP (4 nm EUV) foundry node, which offers improvements over the TSMC N6 DUV node the current cIOD is being built on. A key area of focus for AMD will be the memory controllers, which will be updated to support higher DDR5 memory speeds using technologies such as CKD. You can currently run a "Granite Ridge" processor with memory speeds of up to DDR5-8000 but using a 1:2 clock divider is engaged between FCLK and MCLK, with 1:1 speeds being limited to around DDR5-6400. The new memory controllers will look to increase speeds with 1:1, and unlock speeds beyond 10000 MT/s with 1:2.
Then there's the matter of AI acceleration, and the new cIOD will present AMD with the opportunity to implement at least a 50 TOPS-class XDNA 2 NPU. Intel received flack for giving its "Arrow Lake" processors a 16 TOPS-class NPU that doesn't meet Copilot+ requirements, and the company is probably working to fix this in "Panther Lake," and so if AMD decides to implement an NPU on the cIOD for "Olympic Ridge," we predict it will be at least 50 TOPS-class.
View at TechPowerUp Main Site | Source
