Intel Meteor Lake Could Bring Back L4 Caches

[AleksandarK]

In the latest Linux Kernel patches, Intel engineers are submitting initial support for Meteor Lake processor generation, with some interesting potential features. In a patch submitted yesterday, the Intel engineer noted, "On MTL, GT can no longer allocate on LLC - only the CPU can. This, along with the addition of support for ADM/L4 cache, calls a MOCS/PAT table update." What this translates to is that starting from Meteor Lake, the integrated graphics can no longer allocate on the last-level cache (LLC), the highest numbered cache accessed by the cores before fetching from memory. Instead, only the CPU cores can allocate to it. Even more interesting is the mention of the Meteor Lake platform's level 4 (L4) cache. For the first time since Haswell and Broadwell, Intel may be planning to bring back the L4 cache and integrate it into the CPU.

Usually, modern processors use L1, L2, and L3 caches where the L1 version is the fastest and smallest, while the others are larger but slower. The inclusion of L4 caches often is unnecessary, as this type of cache can consume a big area on the processor die while bringing little benefit, translating to the cost of manufacturing drastically soaring. However, with Meteor Lake and its multi-die tile design, we wonder where the L4 cache will end up. We could see integration into the base tile, which holds the compute cores and essential compute elements. This makes the most sense since the logic needs access to fast memory, and L4 could improve the performance in specific applications.



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[Daven]

Intel could also stack cache on top like AMD but consider it level 4 instead of an extension of level 3 cache.

 

[SOAREVERSOR]

Intel could also stack cache on top like AMD but consider it level 4 instead of an extension of level 3 cache.

Given the drawbacks of AMDs solution for everything but gaming (and even then not all games can truly use it) there's little point in that approach especially if you want to sell to business, enterprise, content creators, and everyone not a gamer.

 

[Daven]

Given the drawbacks of AMDs solution for everything but gaming (and even then not all games can truly use it) there's little point in that approach especially if you want to sell to business, enterprise, content creators, and everyone not a gamer.

Stacking chips has nothing to do with what you said. The limited improvement you describe in some apps like games is due to more cache and the premise of the article is that Intel is adding more cache. I’m just guessing how they would add more cache given limited space on the die.

Are you arguing that the L4 cache premise of the article is not happening because its not a good solution and Intel will NOT increase cache sizes or add cache levels whether stacked or not?

 

[Vya Domus]

Given the drawbacks of AMDs solution for everything but gaming (and even then not all games can truly use it) there's little point in that approach especially if you want to sell to business, enterprise, content creators, and everyone not a gamer.

There is nothing wrong with the 3D v-cache designs for products targeted outside gaming, 7950X3D for example is still very much on the top of the charts in professional applications.

 

[BoboOOZ]

Given the drawbacks of AMDs solution for everything but gaming (and even then not all games can truly use it) there's little point in that approach especially if you want to sell to business, enterprise, content creators, and everyone not a gamer.

Cache is cache, whether you stack it vertically or place it horizontally it works just the same, and it benefits some applications more than others, as all types of optimizations. Some games benefit a lot from a large cache, but not all do, and some other applications also benefit, but not all do.

 

[hs4]

Read the Chips and Cheese's article titled "Hot Chips 34 – Intel’s Meteor Lake Chiplets, Compared to AMD’s". It was expected that new kind of chache would be placed in the Meteor lake because iGPU no longer share the ring bus and L3 with other CPU cores as a result of division of tiles. In other words, this is forced.

As of Hot Chips 34 last summer, Intel had not been decided what would be placed on the base tile. So that many people thought it would be a waste to make it just an interposer, and there have been many predictions that a new cache would be placed here. However, Foveros with solder ball bonding are not fast enough to place L3, so their use will be quite limited (V-Cache is bonded with a copper pillar that is a generation ahead of solder ball, and Intel will not make it available until later this year.) The base tile is 22FFL, so cache density will also be an issue.

Instead, the new cache to be placed in the GPU tile may be treated as L4. Also, since the media slice is presumed to be on the SoC tile, we cannot rule out the possibility that L4 is also on the SoC tile.

AMD's 780M has low performance for the number of CUs and DDR5 seems to be the bottleneck, caches like Infinity Cache will solve that to some extent.

After next year, Foveros Direct could get fast enough to join L3, so Intel could get a virtually free VCache on the base tile. However, I do not expect that to happen with Arrow lake.

 

[Daven]

Read the Chips and Cheese's article titled "Hot Chips 34 – Intel’s Meteor Lake Chiplets, Compared to AMD’s". It was expected that new kind of chache would be placed in the Meteor lake because iGPU no longer share the ring bus and L3 with other CPU cores as a result of division of tiles. In other words, this is forced.

As of Hot Chips 34 last summer, Intel had not been decided what would be placed on the base tile. So that many people thought it would be a waste to make it just an interposer, and there have been many predictions that a new cache would be placed here. However, Foveros with solder ball bonding are not fast enough to place L3, so their use will be quite limited (V-Cache is bonded with a copper pillar that is a generation ahead of solder ball, and Intel will not make it available until later this year.) The base tile is 22FFL, so cache density will also be an issue.

Instead, the new cache to be placed in the GPU tile may be treated as L4. Also, since the media slice is presumed to be on the SoC tile, we cannot rule out the possibility that L4 is also on the SoC tile.

AMD's 780M has low performance for the number of CUs and DDR5 seems to be the bottleneck, caches like Infinity Cache will solve that to some extent.

After next year, Foveros Direct could get fast enough to join L3, so Intel could get a virtually free VCache on the base tile. However, I do not expect that to happen with Arrow lake.

Now that’s the most informative comment I have ever read on the internet. Thanks for the info!

 

[Minus Infinity]

There is nothing wrong with the 3D v-cache designs for products targeted outside gaming, 7950X3D for example is still very much on the top of the charts in professional applications.

In a few apps like cryptography and some video encoding etc. It's still behind in most cases of relevance to normal users unless running in PBO max mode. For the 7950X I could care less about the improved fps in a few games, but the efficiency is really good and probably worth the loss in productivity scores overall.

 

[R0H1T]

Given the drawbacks of AMDs solution for everything but gaming (and even then not all games can truly use it) there's little point in that approach especially if you want to sell to business, enterprise, content creators, and everyone not a gamer.

What drawbacks? Azure was the first one to employ these chips & they work great in DC/HPC just as well

AMD Releases Milan-X CPUs With 3D V-Cache: EPYC 7003 Up to 64 Cores and 768 MB L3 Cache​