No it doesn’t?
1) Clamshell 16GB model and don’t release an 8GB
2) Design it with a 192-bit bus in the first place
3) Source other IC or memory types allowing for higher memory capacity overall.
The point, and it’s sad I have to restate this, is the card should have never released (5060ti and 9600XT) with 8GB variants. It has absolutely nothing to do with how it’s possible, take your semantics somewhere else.
1) Increases logistical cost (8 * 2GB IC's), especially capacitors near back side IC's.
The entire point of a smaller die is to incrementally cram more performance (SM/CU) into a smaller package and allow more the same or better performance relative to previous generation. Yield per wafer obviously matters too.. AMD/NVIDIA can extract way more 200mm2 units than stuff nearing 400mm2 per 300mm wafer.
MC layout is sacrificed for more SM/CU.
The obvious adaptation for "low end" is 3/4GB IC on GDDR7. NVIDIA is just being greedy as hell right now.
Both AMD and NVIDIA have the same goals and motives. It's clear as day how they're segmenting the newer "60" classes. I'm sorry, it's not 2016 anymore.
128 (4 x 32) bit is the new "192 bit" config for future cards.
2) AMD completely skipped the "mid tier" and went a little bigger this generation via NAVI 48 (357mm2). It's almost same size as GB203 (378mm2), but more dense transistor wise.
Last "big" monolithic AMD was 520mm2 on TSMC 7nm, 80 CU. A lot of the density increase on N48 seems to be RT related, same should be true for Navi44.
In reference to the 5060 TI specifically, 128bit @ 448GB/S with 28GB/s GDDR7 shouldn't even exactly bottleneck a card at 1080/1440P. I guess I'm just tired of this "bit bus" non sense, when bandwidth and cache are the only things that matter in this aspect. You're just mad you're getting less relative to legacy segmentation and I can understand that.
Both 5060 TI (36 SM) and 9060XT (32CU) are both inherently weaker, at lease relative to what NAVI 48 (64 CU) and GB203 (84 SM) are. All of these are full enabled and used interchangeably with Quadro's and whatever AMD brands theirs as.
AMD using GDDR6 puts them behind NVIDIA in the real world bandwidth metric, regardless of double sided PCB implementation. It will end up more expensive long term as GDDR6 will start to phase out. They dug themselves in a hole, but prob don't care as much given sales have been good with Navi48.
3) What other IC's? They're not gonna use HBM again (SoC design regardless) and GDDR6X is a NVIDIA/MICRON deal. Memory controller on AMD side is designed for GDDR6... Were kind of stuck with 2GB config in 8/16 layouts given die layout on AMD's end.
I agree with you... 5060 TI shouldn't have released with 8GB
or 16GB. It should have been delayed and launched with 3GB IC (12GB). 448GB/s with inherit cache pool won't bottleneck a 36 SM card.
Even if AMD launches a 192 bit GDDR6 model (9070 GRE? cut from N48?) the bandwidth would be almost even with NVIDIA on 128 bit via GDDR7.
Semantics are fine. It paints the why. Hurr durr we need 192 bit means nothing.