5950x and PBO overheated something or busted custom loop?

[Chomiq]

Tiachi ordered. Now we wait.

Found a video that suggest the extra 4 pin can be used to help supply PCIe power if your using a lot of PCIe devices.

If it's there, plug it in.

 

[A Computer Guy]

If it's there, plug it in.

LOL, Researching earlier I think I found you had made this comment on another thread.

Curious about this I checked the Taichi x570 manual

although I've seen in other manuals they say it's optional

 

[Chomiq]

LOL, Researching earlier I think I found you had made this comment on another thread.

Curious about this I checked the Taichi x570 manual
View attachment 256848
although I've seen in other manuals they say it's optional

What's better:
- having it plugged in from the start
- spend x hours/days on troubleshooting only to find out all what was needed was to plug it in
?

 

[A Computer Guy]

LOL, Researching earlier I think I found you had made this comment on another thread.

Curious about this I checked the Taichi x570 manual
View attachment 256848
although I've seen in other manuals they say it's optional

In my Master SLI/ac manual it's even more ambiguous

 

[Valantar]

Some motherboards require these to be connected, and those will not boot without them (or will throw an error). Others do not, and will thus work fine as long as the 8+pin provides enough power - which it does for any Ryzen CPU, no matter the settings or overclock, as an EPS cable can provide 4*7A at 12V or 336W. Even if its a crap tier PSU with weak wiring and connectors it should do 5A per pin, which is still 240W - plenty for any Ryzen, even including VRM conversion losses.

 

[A Computer Guy]

What's better:
- having it plugged in from the start
- spend x hours/days on troubleshooting only to find out all what was needed was to plug it in
?

Not debating your sound logic it's just fascinating how it seems in the AM4 ecosystem there is so much confusion around this connector.
A vast majority of posts I come across pretty much state you don't need it "it's for extreme overclocking", "your system will run fine without it" etc...
Would it have been so hard for manufacturers to have been more specific in their manuals? In some cases they actually do say at least it's "optional".

Being one not to settle for ambiguity, coming across that L1 video peeked my curiosity in what I thought was a settled topic, as it's the first counter statement I've seen that might make sense to what everyone else was saying regarding the 4 pin connector. So it either is or is not involved in supplying additional PCIe power or perhaps some board manufactures find cleaver ways to use this connector that isn't just used for CPU power. I'm kind of curious to find any confirming evidence either way besides just what people say.

That makes sense

You know, I wonder if this ties into the issues some people had with USB device disconnects due to the PCI-E bus resetting (AGESA updates reduced it, but it's still semi common - i've only ever caused it with a damaged PCI-E riser cable and a crappy asmedia USB-C port)
High power draw PCI-E/USB devices, combined with someone skipping an extra power connector...
Even if they're seperated, It's given me something to think about next time someone brings that issue up (are they using all the power connectors, extensions, etc. I have a 4 ->8+4 dubious splitter here in the spare parts bin)

I can't say I've had a lot of USB problems but I did have USB problems on my motherboard when putting some good stress on it (multiple transfers to hard drives using USB power and such) going on at the same time.

 

[Valantar]

So it either is or is not involved in supplying additional PCIe power or perhaps some board manufactures find cleaver ways to use this connector that isn't just used for CPU power. I'm kind of curious to find any confirming evidence either way besides just what people say.

It is of course entirely possible for the cpu VRM and the PCIe 12V to be on the same power plane, however AFAIK this isn't done. I wouldn't be surprised if the ATX spec mandated cpu power on its own plane, as avoiding noise on that power plane is crucial for system stability.

So: it is theoretically possible that an additional 4-pin supplies additional PCIe power, but in all cases I know of it is only there to supply additional CPU power for overclocking, and I haven't heard of a single example of it doing more. Boards with additional PCIe power tend to use either 4-pin Molex or 6-pin PCIe plugs for this.

 

[tabascosauz]

Not debating your sound logic it's just fascinating how it seems in the AM4 ecosystem there is so much confusion around this connector.
A vast majority of posts I come across pretty much state you don't need it "it's for extreme overclocking", "your system will run fine without it" etc...
Would it have been so hard for manufacturers to have been more specific in their manuals? In some cases they actually do say at least it's "optional".

Being one not to settle for ambiguity, coming across that L1 video peeked my curiosity in what I thought was a settled topic, as it's the first counter statement I've seen that might make sense to what everyone else was saying regarding the 4 pin connector. So it either is or is not involved in supplying additional PCIe power or perhaps some board manufactures find cleaver ways to use this connector that isn't just used for CPU power. I'm kind of curious to find any confirming evidence either way besides just what people say.


I can't say I've had a lot of USB problems but I did have USB problems on my motherboard when putting some good stress on it (multiple transfers to hard drives using USB power and such) going on at the same time.

If for some reason you're worried about board being picky/not trusting your EPS cables, it's real easy just to plug in the extra 4-pin. You really don't lose anything - just don't expect to gain anything either. I'm just a bit biased against stuff that's unnecessary, as I'm sure you understand with your NR200 the massive headache from just adding an extra EPS in an SFF case.

But speculating that it provides power to GPUs or solves the USB bug is just a whole new level of ridiculous. From the cable to the connector to the board, not what any of them are designed for. I suppose you could ask like luumi or bz to probe with their multimeter but I doubt anyone would waste their time proving that the CPU power plane stays in the CPU power plane. This is exactly like hoping an ECU swap in your car will make Android Auto lag less - they're entirely different, separate entities.

And how would anyone even prove anything with the multimeter? Every VRM has losses - input at EPS =! output to the socket. If there are significant enough losses from EPS to show up measurably on some other rail/power plane, the board has a big problem on its hands...

...and as to the potential voltage stabilization issue, if your board can't stabilize Vcore on a single EPS, then LLC is defective (personally seen on my Aorus). Second EPS connector is way down the list of troubleshooting priorities there.

Especially on lower layer count boards, you can literally see the footprint of the CPU power plane on the front and back of the VRM, from the EPS connector(s) leading to the socket. It's not huge and doesn't really cover too much of the board.

 

[A Computer Guy]

If for some reason you're worried about board being picky/not trusting your EPS cables, it's real easy just to plug in the extra 4-pin.

I don't think I have an extra 4 pin anyway but I haven' been really worried about it since 2018 since I'm not really doing any kind of extreme overclocking, just extreme brick making recently.

You really don't lose anything - just don't expect to gain anything either. I'm just a bit biased against stuff that's unnecessary,

I agree. If they used the money from putting on a useless extra connector toward some working VRM protection instead I might still have a board today. But then again I did end up buying into some fancy RGB so that might make me a hypocrite in that regard.

as I'm sure you understand with your NR200 the massive headache from just adding an extra EPS in an SFF case.

I can relate although NR200 does seem kind of roomy compared to other cases I've seen online.

But speculating that it provides power to GPUs or solves the USB bug is just a whole new level of ridiculous.

Not understanding enough about how MB circuitry is designed I can't say either way - USB is 5v so it's doesn't really make sense to me for a 12v connector to be involved in that unless there is onboard circuitry for that. I could be wrong but I thought the USB power came from the 5v rail(s) of the PSU to the main MB connector.

From the cable to the connector to the board, not what any of them are designed for. I suppose you could ask like luumi or bz to probe with their multimeter but I doubt anyone would waste their time proving that the CPU power plane stays in the CPU power plane. This is exactly like hoping an ECU swap in your car will make Android Auto lag less - they're entirely different, separate entities.

And how would anyone even prove anything with the multimeter?

It was an idea, I'm not an electrical engineer! I had an inner buildzoid voice in my mind at the time of writing imagining a conversation that starts something like "Ok apparently nobody listens to me so I'm going to prove to you idiots this 4 pin connector is complete and utter garbage...well not complete garbage...but yes totally unnecessary etc...".

 

[tabascosauz]

I'm not really doing any kind of extreme overclocking, just extreme brick making recently.

I had an inner buildzoid voice in my mind at the time of writing imagining a conversation that starts something like "Ok apparently nobody listens to me so I'm going to prove to you idiots this 4 pin connector is complete and utter garbage...well not complete garbage...but yes totally unnecessary etc...".

Would be a great thing to have a dedicated video on this. I have nothing to link every time the extra 8-pin topic comes up, because he only talks about it in passing, and linking Youtube timestamps doesn't always work in embed.

Not a hypocrite! Taichi is pretty anti-RGB. No OC Formula for us so Taichi is top of the line for ASRock - I have a usual laundry list of problems with ASRock but I'd feel confident trusting in that board in particular.

Don't be alarmed but because the X570 is an early gen board it uses SiC634 Vishays and ISL69147 (Z390/X570 era controller) that don't have a OTP flag I think ASRock switched to SiC654 and RAA229004 for the B550 generation both of which have a wider safety set. But 12 x 50A is a common and very strong setup, won't break a sweat. The Strix-A and Strix-F boards are in the exact same boat with12 x SiC639, all tough boards. I think your X470 K4 must have been an anomaly.

 

[A Computer Guy]

Would be a great thing to have a dedicated video on this. I have nothing to link every time the extra 8-pin topic comes up, because he only talks about it in passing, and linking Youtube timestamps doesn't always work in embed.

Not a hypocrite! Taichi is pretty anti-RGB. No OC Formula for us so Taichi is top of the line for ASRock - I have a usual laundry list of problems with ASRock but I'd feel confident trusting in that board in particular.

Don't be alarmed but because the X570 is an early gen board it uses SiC634 Vishays and ISL69147 (Z390/X570 era controller) that don't have a OTP flag I think ASRock switched to SiC654 and RAA229004 for the B550 generation both of which have a wider safety set. But 12 x 50A is a common and very strong setup, won't break a sweat. The Strix-A and Strix-F boards are in the exact same boat with12 x SiC639, all tough boards. I think your X470 K4 must have been an anomaly.

The Taichi and CPU block arrived. Looks like I got the updated model with the fixed internal USBC header. Rev 1.06.

For a quick test I popped in my NVMe and it booted my old OS just fine after some driver changes although I think it will probably deactivate my Windows10 when it comes back online.

For the moment I'm going t setup the Taichi with my 3950x until after I get a chance to test the 5950x. It won't be till sometime next week before I know if the 5950x is really damaged. If it's good then swapping it out will be fast and easy with the cpu block compared to the monoblock.

I'll post some pictures tonight.

Test Boot. Only 2 ram sticks, using my spare graphics card rx5500, and spare cooler H100i Pro. (my original cooler before my custom loop), and used some 5yr old artic silver 5 so I can save the good stuff for the final configuration. Borrowed my 10yr old's kano keyboard.

Also I popped in my old NVMe drive and hooked up the 80mm fan because the zero rpm mode on the card let's it get hot.

A quick run of CB20, I can see I am getting a slightly better score than when my ram was OC to DDR4-3200. I didn't bother OC ram for this test.

Temps look ok after the run

Here you can see the fixed USB-C header on my revised board

The mighty 40mm noctua cooling GPU stuck in zero fan mode

New CPU water block

Hope everyone enjoys the pictures.

 

[A Computer Guy]

Had to wash my rad to get the burnt plastic/pcb smell out.

Ugh oh! I didn't expect that! What to do?

RAD cleaned and air blown dry. Laterally smells like a baby considering I washed it with Aveeno Baby Wash. ( yes I closed the ports first - duh! )

 

[freeagent]

I like the smell of Aveeno

Looks nice and new again

 

[A Computer Guy]

Time to get serious about cable management

who needs those fancy click together fans anyway

Whoever designed the distroplate wasn't thinking about the case design. This squished cable still bothers me to this day.

So that was what the bigger side of the key was for...

pressure testing

I like the smell of Aveeno

Looks nice and new again

Works great. I was doubting if it would be enough but it gets the job done with 3950x/5950x and a rx5700.
I guess they don't make these ones anymore. Now they have ones with these white caps.

 

[A Computer Guy]

Tonight's activity .. some ram overclocking with x570 Tiachi on a new ram kit before I do my reassembly back into the 011D with the new CPU water block. If this works nicely I have future expansion to 128GB.

Before I realized there was the Ryzen overclocking guide I made and used a spreadsheet like this. The idea was to try and first and scale the frequency up close to the timings in ns then trim the timings down. This kit really didn't like to try anything DDR4-3400 and over so I tried to go the other way around and simply improve the timings to something that resembles a decent DDR4-3200.

 

[Pictus]

Tonight's activity .. some ram overclocking with x570 Tiachi on a new ram kit before I do my reassembly back into the 011D with the new CPU water block.

I had defective RAM that MenTest86 was not able to find errors, but more demanding RAM tests was able to.
Y-cruncher is one of the most demanding tests around http://www.numberworld.org/y-cruncher/
The #14 is for RAM, Press 1 + ENTER, 8 + ENTER, 14 + ENTER, 0 + ENTER



Some people may like, AMD Overclocking - Curve Optimizer Explained

To avoid problems with the Curve Optimizer, better set the Processor
power management to 15% or more, but not zero.

As we are talking about Power Options, I like this tweak too.

 

[Valantar]

I had defective RAM that MenTest86 was not able to find errors, but more demanding RAM tests was able to.
Y-cruncher is one of the most demanding tests around http://www.numberworld.org/y-cruncher/
The #14 is for RAM, Press 1 + ENTER, 8 + ENTER, 14 + ENTER, 0 + ENTER



Some people may like, AMD Overclocking - Curve Optimizer Explained

To avoid problems with the Curve Optimizer, better set the Processor
power management to 15% or more, but not zero.

As we are talking about Power Options, I like this tweak too.

Setting the minimum processor state higher to "avoid problems" is ha poor, hacky workaround. Do it the proper way, test through usage, identify failing cores through Event Viewer if the system crashes, reduce the CO offset for that core until crashes cease. The main challenge with CO is instability at idle due to the curve offset being too aggressive at very low clock levels, which this minimum state offset works around, but that isn't actually stable, you're just forcing your CPU to waste energy to avoid crashes. Identifying stable individual core offsets will take a few days, but it's a really simple process overall.

 

[A Computer Guy]

I had defective RAM that MenTest86 was not able to find errors,

I use MemTest86 as just the 1st step in testing. If any errors happen here it's easy and quick enough to adjust and retry a single pass before more extensive testing.


( updates from the original thread below since the motherbaord blowout and swap in x570 Tiachi )

The 5950x posts on the x570! Running initial memtest to see if memory controller is ok. - Memtest ok

Did a few quick all core tests using 7zip. All cores seem to be hitting the same frequencies (4.5GHz) as before the motherboard burnout.

CPUz is benching just shy was what it was doing before but that might be due to using different RAM this time around. (I haven't retuned it for 5950x)

More testing to be done later today.

 

[A Computer Guy]

Updates...

Testing is going well. About 1/5th in the way of a 350GB 7zip test 2nd round of testing with 7zip. The first round was getting WHEA correctable memory errors so I know the ECC is working with this new 3200 ram kit I have. I had to back off the ram tighter timings OC for now and retune it later. Unfortunately I can't seem to obtain any stable higher frequency with this Nemix Ram.

CPU holding steady at 67c, vrm 47c, ram at 46c (1.2v), chipset 51c, room temp is about 32c. Core utilization is about 4.575MHz on all cores.

• Used the thermal grizzly paste this time around. seems to be a bit better.
• The Quantum Velocity block is doing much better than the prior monoblock with FULL coverages on the IHS now and temps are bit lower.
• The VRM heatsinks are doing their job well.
• No smells of burning plastic or pcb.
• Had the opportunity to redo cable management.
• Saved 40 dollars by not getting the RGB CPU block, reused the RGB from the old monoblock instead.

Issues

• The ASRock rgb controller won't seem to recognize my changes to settings and is stuck on red or rainbow puke depending on the setting. This may be because of the prior polychrome installation with my previous board. Even though I uninstalled and reinstalled it I suspect my prior boards options are stuck in there somewhere. Still contemplating a full OS reinstall.
• Had a tragic USB plug malfunction with the mainboard that I was thankfully able fix and recover without RMA. (will post pictures, ! Beware of USB connectors with holes on the sides ! )
• Need to get 1 d-rgb extension cable for the distroplate because the connector is now too far away.

Will post more pictures of reassembly perhaps later this evening if anyone is interested.

 

[A Computer Guy]

Some reassembly pictures

backplate for Velocity waterblock

Mounts

Fittings

Test fittings. Needed to change the GPU input fitting to a 45 degree otherwise the existing tubes were good to reuse.

Pressure testing the CPU block

Bottom fan cable management for excess cable

Whole system pressure test

System at a glance. I tried using a spare EK-LED strip from my monoblock however it only showed green LED's no matter what settings were used so I ended up pulling out the strip. Oh well. Perhaps later I'll pull the LED strip from the monoblock and reuse it here in the CPU block.
I had a bit of trouble with the polychrome software not changing the colors so I updated the firmware to fix the issue.

Cinebench test run. 53c not bad. better then what I did before.

Close up of the better cable management paid off.

Custom foam cutout to fill the empty gap and help airflow pressurize in the 011D.

The USB-C port just barely fit. Thanks ASRock for having fixed the position of the port.

Despite hours of cable management and bundling slack it still looks like a mess. Under the Commander Pro zip tied to the cable management bar is a corsair 2 bay SSD mount.

The darn USB keyboard adaptor got stuck in the USB port. Can you tell which port it was?

I'll show you here... The USB dongle had two cutouts (one on each side) the inside tabs of the usb port caught on them preventing the plug from coming out. I ended up tearing out the dongle insert leaving the plug casing stuck inside. Then I had to crush the dongle casing to pull it out and the tabs from the port ended up folding out in the process. (forgot to take a picture of that) Using a pair of small curved pliers I ended up folding the USB port tabs back in again but you can see the surface bend. I was lucky not to break the port completely.

Also used a sharpie on the edges of the ram PCB to black them out. (learned that from Jay's 2 cents)

 

[A Computer Guy]

Yeah you got it...

I should point out that all settings was done into BIOS. I do not trust any software for this.
For board limits there is actually a "Motherboard" setting for PBO.

You know what the "funny" thing is? All that Current (A) going into CPU in the first 3 screenshots (out of 6) is just a total waste that only stresses the CPU silicon and potentially VRMs (depending the board).
Allow me to state the R23 scores of each run

---------------------------------------

I dont have the screenshots of R23, you have to take my word for it.
Also those were quick settings just to show the idea of PBO limits and CO.
It wasn't a real optimization but rather a demo of it.


1. PBO disabled (PPT:142W, TDC:95A, EDC:140A) with no Curve Optimizer enabled.
Actual avg PPT: 139W, EDC: 138A
R23 MT: 20932

2. PBO on board limits (PPT:900W, TDC:480A, EDC:215A) with no Curve Optimizer enabled
Actual avg PPT: 151W, EDC: 194A
R23 MT: 21060

3. PBO on board limits (PPT:900W, TDC:480A, EDC:215A) with CO from -5 (to best CCD) to -10 (to worst CCD)
Actual avg PPT: 158W, EDC: 203A
R23 MT: 21583

4. PBO on board limits (PPT:900W, TDC:480A, EDC:215A) with CO from -10 (to best CCD) to -20 (to worst CCD)
Actual avg PPT: 165W, EDC: 209A
R23 MT: 22000

--------------------------------

5. PBO on custom limits (PPT:200W, TDC:130A, EDC:160A) , with CO from -5 (to best CCD) to -10 (to worst CCD)
Actual avg PPT: 161W, EDC: 156A
R23 MT: 21875

6. PBO on custom limits (PPT:200W, TDC:130A, EDC:160A) , with CO from -10 (to best CCD) to -20 (to worst CCD)
Actual avg PPT: 164W, EDC: 158A
R23 MT: 22021

7. PBO on custom limits (PPT:160W, TDC:115A, EDC:135A) , with CO from -10 (to best CCD) to -20 (to worst CCD)
Actual avg PPT: 159W, EDC: 134A
R23 MT: 22176

So I must be a glutton for punishment and decided to try PBO again. (without curve optimizer for now)

PBO disabled (PPT:142W, TDC:95A, EDC:140A) with no Curve Optimizer enabled.
Actual avg PPT: 124W, TDC: 93A, EDC: 136A
R23 MT: 25206

Using the UEFI/BIOS I got the board limits and out of extreme paranoia set the temp limit to 75c.
Then a ran with the board limits and did some tests to see where PPT, TDC, and EDC really landed and keeping a close eye on VRM and CPU temps.

PBO on board limits are (PPT:1000, TDC:540A, EDC:540A, and 75c limit)
Actual avg PPT: 120W, TDC: 85A, EDC: 184A
R23 MT: I didn't capture my score but it was worse

Pretty much every benchmark was worse and temps were nothing extraordinary.

The I tried to dial everything back to something that seemed to be sane, setting the default for PPT, giving some slack to TDC from the default, and arbitrarily lowering EDC from the default.

PBO on dialed in limits (PPT:142W, TDC:115A, EDC:120A, and 75c limit)
Actual avg PPT: 142W, TDC: 108A, EDC: 120A
R23 MT: 26458

When I did this I discovered PPT is now hitting it's limit and CB score increased a bit.
Knowing enough to be dangerous I upped my PPT to 160.

PBO on dialed in limits (PPT:160W, TDC:115A, EDC:120A, and 75c limit)
Actual avg PPT: 152W, TDC: 115, EDC: 120A
R23 MT: 27100

So some knowledge I have now
- So EDC past 145A kills boost clocks so that is a no go.
- For all core loads: Only higher effective clocks = higher performance, and this can be achieved at lowest possible temp with a reasonable EDC and most likely lower than the stock 140A(EDC).

How might you recommend I proceed to balance out PPT and EDC for the best outcome?
I suspect I need to raise these values one at a time to find the right temperature / performance balance correct?

Below are screenshots of my last run just to provide some more info to my progress so far

 

[Zach_01]

So I must be a glutton for punishment and decided to try PBO again. (without curve optimizer for now)

PBO disabled (PPT:142W, TDC:95A, EDC:140A) with no Curve Optimizer enabled.
Actual avg PPT: 124W, TDC: 93A, EDC: 136A
R23 MT: 25206

Using the UEFI/BIOS I got the board limits and out of extreme paranoia set the temp limit to 75c.
Then a ran with the board limits and did some tests to see where PPT, TDC, and EDC really landed and keeping a close eye on VRM and CPU temps.

PBO on board limits are (PPT:1000, TDC:540A, EDC:540A, and 75c limit)
Actual avg PPT: 120W, TDC: 85A, EDC: 184A
R23 MT: I didn't capture my score but it was worse

Pretty much every benchmark was worse and temps were nothing extraordinary.

The I tried to dial everything back to something that seemed to be sane, setting the default for PPT, giving some slack to TDC from the default, and arbitrarily lowering EDC from the default.

PBO on dialed in limits (PPT:142W, TDC:115A, EDC:120A, and 75c limit)
Actual avg PPT: 142W, TDC: 108A, EDC: 120A
R23 MT: 26458

When I did this I discovered PPT is now hitting it's limit and CB score increased a bit.
Knowing enough to be dangerous I upped my PPT to 160.

PBO on dialed in limits (PPT:160W, TDC:115A, EDC:120A, and 75c limit)
Actual avg PPT: 152W, TDC: 115, EDC: 120A
R23 MT: 27100

So some knowledge I have now
- So EDC past 145A kills boost clocks so that is a no go.
- For all core loads: Only higher effective clocks = higher performance, and this can be achieved at lowest possible temp with a reasonable EDC and most likely lower than the stock 140A(EDC).

How might you recommend I proceed to balance out PPT and EDC for the best outcome?
I suspect I need to raise these values one at a time to find the right temperature / performance balance correct?

Below are screenshots of my last run just to provide some more info to my progress so far
View attachment 259846

Thats nice!

Do you care mostly for MT or ST performance?

I would throw in some negative CO and see if I can improve anything with those limits.
Remember that too much negative curve can render the system unstable (*first on idle/low load). Also not all cores can take the same amount of undervolt.

Your guide is the "perf #x/x" order (first number x/x):

(**)Low number can take the lowest negative and higher number the highest negative.

In BIOS (in CO) there are 30 steps (positive or negative).
Each step (negative) reduces voltage by around 3~5mV (0.03~0.05V)
(*) ~5mV at low end curve = when idling or on very low loads (and speeds) and progressively reduces ~3mV on high end of curve = on highest loads (and speeds)

No Ryzen CPU can supply individual voltage to each core. The voltage feed to cores is always 1 value and same for all cores (look at "CPU Core Voltage SVI2 TFN")
So...
Practically, with negative CO you are setting different (higher) speeds on each core on the same voltage on top of the already different speeds AMD evaluated each core (perf #x/).

(**)As you will see on your screenshot the "Core 6 (perf #1/1)" has the highest speed already and "Core 14 (perf #15/16)" the lowest speed

Second perf number #x/x is the order windows scheduler chooses to keep loads mostly. Even on ST or on 2~3 threaded loads all the way up to full MT, the loads are keep moving around constantly but mostly stay on that second order.
This can be confirmed by many factors other than pure (discreet) clocks.
By effective clocks (=hence the C0/1/6 individual core state residency), by individual core temps, individual core loads/utilizations, individual core powers... etc.

I would start with CO -3 steps for the 1st core(s) (core 6 and 2) up to -15 steps for the 16th (core 14)

----------------------------------------

EDIT:
Last but not least...
Enable "CPU Snapshot Polling" in HWiNFO main settings.

 

[A Computer Guy]

Just some more experimenting with PBO before I dive into curve optimizer.
Interestingly in test config #4 the EDC limit was ignored.
My temps were all over the place because of my AC was on and off during the testing

 

[Ferrum Master]

As water cooling veteran... such burst testing doesn't reflect actual usage at all. Those things work fine for air coolers as those are fast at thermal transfer.

Basically what's your aim? My aim is productivity batch jobs in Lightroom, schematic real time simulations and gaming. Basically all of those things will warm up your loop significantly from ambient to some usually 30-42C, depending how long you do things, if you game all night long you warm up the loop and are close to equilibrium and your fans should go rampage.

Basically all your test should be tied to loop liquid temperature worst scenario as you can kill boost on warmer temps giving too much power budged for the CPU, it would look fine in benchmarks but later in actual gaming all temps rising gradually the boost and effective clock will be limited and you do not want it.

 

[A Computer Guy]

As water cooling veteran... such burst testing doesn't reflect actual usage at all. Those things work fine for air coolers as those are fast at thermal transfer.

I must have been going last night. Yea your right, I don't know what I was thinking when I wrote that.

Basically what's your aim? My aim is productivity batch jobs in Lightroom, schematic real time simulations and gaming. Basically all of those things will warm up your loop significantly from ambient to some usually 30-42C, depending how long you do things, if you game all night long you warm up the loop and are close to equilibrium and your fans should go rampage.

My goal is exploration and number chasing at the moment. A 10 minute CB23 run changes my loop temps +2.7 degrees with about 5 minutes to drop back to starting temps with my fans around 1300 rpm.