AMD 5th Gen EPYC "Turin" Pictured: Who Needs Accelerators When You Have 192 Cores?

[Tek-Check]

My ideal Zen 5 desktop:
Zen 5 CCD - 8 (16) cores, 6+ GHz clocks, 15+% IPC
Zen 5c CCD - 16 (32) cores, 5+ GHx clocks, 15+% IPC, 128 MB 3D V cache
Total cores (threads): 24 (48)
Zen 5 IOD - major memory controller improvements (DDR6400+ without going into a lower gear), native USB4, RDNA4 with 4 CUs

Unlikely. RDNA4 will not be ready for Zen5 desktop. It's not even clear whether RDNA3 would replace current RDNA2 iGPU. It's not clear whether there is enough space on IOD for extra 2 CUs. Probably full node shrink is needed for it. Integrated USB4 is more realistic. 8000G SKUs will have integrated two USB4 ports.

Probably doesn't align with known N3P schedule, but if Zen 5 debuts in middle of 2024 then I guess it makes sense for N3E maturity/adoption.

It looks like they cannot fit 12 CCDs with 192 cores on Turin Dense without going to N3 derivative. It will go into the same socket SP5. We will find out in a few months.

 

[Count von Schwalbe]

Random question - does anyone know/think AMD could use the Phoenix(2) die as part of a MCM setup?

Some high-performance cores on a standard CCD and a bunch of Zen4c cores with a decent IGP and RAM controller.

 

[tabascosauz]

Random question - does anyone know/think AMD could use the Phoenix(2) die as part of a MCM setup?

Some high-performance cores on a standard CCD and a bunch of Zen4c cores with a decent IGP and RAM controller.

But why would they? It's already a CPU/SoC in itself. The whole reason for there to be a IO die in chiplet Ryzen is to complete the package as a "SoC". Put Phoenix on shitty IFOP and link it to other dies, and Fabric/UMC automatically suffers, it's the monolithic type Fabric connection that makes it better perf/latency.

If you mean using Phoenix to put cores inside the IO die (like Intel is doing for Meteor Lake), it's an idea, but AMD has lots of work to do to make its Ryzen chiplet design more efficient. Currently it's just a cost saver and is an order of magnitude worse than its own Navi31 Fabric and Intel EMIB/Foveros. Whole point of island E-cores is to enable shutting down the entire compute die for power. IFOP is way too primitive.

If AMD is going to make Strix Halo, disaggregation is already a requirement. Costs/yields already forced Navi31 that way, it will happen eventually for APUs.

 

[Minus Infinity]

Seems simple:
Italy

How will he react when Zen 6 comes out, which is called Venice? I mean it could be a beach in LA I guess.

Nobody will use N3 (original), it's a shit experiment that only Apple signed up for, and will be dead node as soon as Apple stops using it. All other N3 customers will start on N3E or N3P, which are just starting production. So there's no "freed up capacity".

Nobody will be using N3 for this product either b/c they will pay $$$$ out the ass for all these CCDs. Neither do they need N3's characteristics - server clocks low, dense core probably even lower. At least until N3E/N3P becomes a mature, affordable node (like N6 was last year, like N5 was this year, like N4 is becoming now).

Yeah that's N3B you are referring to and it's widely panned for the miserable improvements in density and power scaling and zero improvement in SRAM, all while costing a bomb per wafer. N4P(X) is basically as good and costs way less per wafer and why AMD will use that for desktop. Most rational companies are waiting for N3E or N3P except of course Apple who just had to crow about being first on 3nm and used N3B. Which is probably why M3 has regressed a bit in efficiency compared to M2.

 

[Count von Schwalbe]

But why would they? It's already a CPU/SoC in itself.

Keeping the IMC on the latest node, and allowing for X3D cores paired with a lower spec of c-cores than the full dense CCD.

Put Phoenix on shitty IFOP and link it to other dies, and Fabric/UMC automatically suffers, it's the monolithic type Fabric connection that makes it better perf/latency.

A decoupled Fabric clock with DDR5 would have much benefit in that regard. My understanding is that the 7nm IMC is the weak point on current Zen 4 offerings, not the Fabric.

If AMD is going to make Strix Halo, disaggregation is already a requirement. It will happen eventually for APUs.

I dunno about that. Fire Range with a new IMC/iGPU combination is a reasonable assumption, but the disaggregation is already there with Dragon/Fire Range. The only new thing about Strix Halo is the doubled memory interface and the ridiculous GPU - which I have a slight difficulty believing.

 

[tabascosauz]

A decoupled Fabric clock with DDR5 would have much benefit in that regard. My understanding is that the 7nm IMC is the weak point on current Zen 4 offerings, not the Fabric.

I dunno about that. Fire Range with a new IMC/iGPU combination is a reasonable assumption, but the disaggregation is already there with Dragon/Fire Range. The only new thing about Strix Halo is the doubled memory interface and the ridiculous GPU - which I have a slight difficulty believing.

That's not how that works, and incorrect assumption. Even the AM4 chiplet UMC has always been strong, since Matisse. The IFOP holds back performance and latency at the exact same freq/timings compared to monolithic. And the monolithic UMC is just better - you can make the argument that it is also newer and improved on design, but bottom line is IFOP is and will always be a cheap solution until AMD puts more effort into its chiplet CPUs (like they do for GPUs). On AM5 with pure memory heavy workloads you already run out of Fabric bandwidth somewhere north of 12 cores.

Dragon Range isn't even an APU, it's a minimal effort repackaging of Raphael for FP7/FP8 without an IHS, and has the same shit iGPU. Has nothing to do with producing Strix Halo.

 

[TumbleGeorge]

The Strix Halo seems too illegitimate to me even with a 256 bit memory interface unless it can run DDR5 12600 and has one available at a reasonable price at launch. Only DDR5 at that speed would provide enough bandwidth to not be too slow for a full 40 CU. So, either it won't exist or it won't be more than 20-24 CU. Or there will be local memory? All this guesswork and walls of text is getting to me and I wonder what the purpose of such a product was leaked on the internet?

 

[tabascosauz]

Yeah that's N3B you are referring to and it's widely panned for the miserable improvements in density and power scaling and zero improvement in SRAM, all while costing a bomb per wafer. N4P(X) is basically as good and costs way less per wafer and why AMD will use that for desktop. Most rational companies are waiting for N3E or N3P except of course Apple who just had to crow about being first on 3nm and used N3B. Which is probably why M3 has regressed a bit in efficiency compared to M2.

At least N3E does come with the electrical improvements even if it makes 0 improvement in SRAM vs. N5, but yeah, just not seeing a good reason for EPYC to move to N3 at this time. Maybe there is some merit to the space argument, but considering the small density improvements and zero SRAM scaling, hard to see how N4P vs N3E would be "make or break" for physically fitting the CCDs in there.

Not to mention, massive server IO die takes up most of the space and will also undoubtedly change if the node changes.

The Strix Halo seems too illegitimate to me even with a 256 bit memory interface unless it can run DDR5 12600 and has one available at a reasonable price at launch. Only DDR5 at that speed would provide enough bandwidth to not be too slow for a full 40 CU. So, either it won't exist or it won't be more than 20-24 CU. Or there will be local memory? All this guesswork and walls of text is getting to me and I wonder what the purpose of such a product was leaked on the internet?

I don't disagree, most of the leaks probably came from MLID lmao

But even if it's not 40CU, the writing is on the wall for monolithic APU. Regardless of Meteor Lake, Intel is no longer as constrained by die size the same way AMD has been. Just remains to be seen what high perf interconnect solution AMD is planning for chiplet APUs.

 

[GreiverBlade]

My ideal Zen 5 desktop:

Zen 5 CCD - 8 (16) cores, 6+ GHz clocks, 15+% IPC

Zen 5c CCD - 16 (32) cores, 5+ GHx clocks, 15+% IPC, 128 MB 3D V cache

Total cores (threads): 24 (48)

Zen 5 IOD - major memory controller improvements (DDR6400+ without going into a lower gear), native USB4, RDNA4 with 4 CUs

not ideal desktop, but rather ideal mobile

although since Z4c/Z5c are not like Intel E core, it would be interesting to see it in desktop

 

[Count von Schwalbe]

Dragon Range isn't even an APU, it's a minimal effort repackaging of Raphael for FP7/FP8 without an IHS, and has the same shit iGPU. Has nothing to do with producing Strix Halo.

Perhaps I misunderstood what you meant by disaggregation.

 

[Daven]

not ideal desktop, but rather ideal mobile

although since Z4c/Z5c are not like Intel E core, it would be interesting to see it in desktop

Don’t forget that Zen 4c is not for low power or efficiency. Its meant for high core count chiplets which is why they are designed for 128 core server CPUs for the cloud.

 

[Minus Infinity]

not ideal desktop, but rather ideal mobile

although since Z4c/Z5c are not like Intel E core, it would be interesting to see it in desktop

Which won't happen anytime soon. AMD has already presented arguments why it sees no need for dense cores on desktop where power is not an issue. Would a 12 core 8 Zen 5 + 4 Zen 5c be really any cheaper than a 12 Zen 5 core part. MLisD argued they should do a 8 Zen 5 + 16 Zen 5c 8960X but AMD said it won't happen when he asked them about the possibility as they don't see a point at this stage where software is still way behind hardware in supporting high core counts.

 

[GreiverBlade]

Which won't happen anytime soon. AMD has already presented arguments why it sees no need for dense cores on desktop where power is not an issue. Would a 12 core 8 Zen 5 + 4 Zen 5c be really any cheaper than a 12 Zen 5 core part. MLisD argued they should do a 8 Zen 5 + 16 Zen 5c 8960X but AMD said it won't happen when he asked them about the possibility as they don't see a point at this stage where software is still way behind hardware in supporting high core counts.

oh, don't get me wrong ... i know AMD said hybrid only has place in mobile (or server if full high count 4c/5c ) which is way more logicall than Intel ... after all AMD did not need hybrid, unlike Intel, to stay competitive or efficient (efficient? in power consumption?)

it was never about core dense CPU on desktop at least for me, it was for the person i quoted

 

[Vayra86]

it was never about core dense CPU on desktop at least for me, it was for the person i quoted

Not even for Intel for several decades, until some competitor suddenly got into chiplets. Yeah, that silly glue, Intel...

How will he react when Zen 6 comes out, which is called Venice? I mean it could be a beach in LA I guess.

Venice is just another lake with streets

 

[Count von Schwalbe]

Venice is just another lake with streets

City Lake, the new AMD/Intel collaboration...

 

[uuee]

How will he react when Zen 6 comes out, which is called Venice?

They already had a Venice