AMD "Big Navi" GPU Die Pictured? Allegedly Measures 536mm²

[iO]

You can't estimate the size of a chip from the back of the board. I don't know why you seem to believe that estimating the size of a chip is such a tremendous task, as soon as you have a picture of the chip with components around it the cat is out of the bag.

You can get an idea of the die size just from the size of cap array but that's often unreliable and usually more like a wild guess of how big or not the die might be

 

[Th3pwn3r]

5700 was a engineering wonder

Lol, good one.

 

[ValenOne]

Also this no reasons...just felt it needed to be inserted into the matter. I wonder if anyone's ever been crazy enough to get that as a tattoo.
View attachment 170865

For GA102 vs TU102, Nvidia doubles the CUDA core count with a minor increase in GPC (incudes a rasterzation unit) count. Your argument is hypocritical.

 

[AnarchoPrimitiv]

Lol, good one.

What's not impressive about a company with a third of the budget able to compete? I think that's really impressive

 

[Th3pwn3r]

What's not impressive about a company with a third of the budget able to compete? I think that's really impressive

You act as if both companies are one trick ponies. They don't just allocate all of their resources into one thing. And as more of a high end user I'm not impressed when someone's best is another's mid grade.

 

[ARF]

5700 was a engineering wonder, pretty much the staff being challenged to make a base chip, medium GPU size and still compete with Nvidia's offerings.

It competes with Nvidia's medium sized GPUs. Which have all the CUDA and RT hardware and still have the same number of transistors.

5700 is a shrink, try to make it on 16nm.

 

[TheoneandonlyMrK]

It competes with Nvidia's medium sized GPUs. Which have all the CUDA and RT hardware and still have the same number of transistors.

5700 is a shrink, try to make it on 16nm.

Wrong, you don't shrink an old architecture and miraculously create a new architecture.

Who the f knows what it competes with, if you have FACT based proof rather than the wafts of air an ass puts out, please ,do show.

 

[Punkenjoy]

Big If there,

but if the infinity cache help to alleviate the performance drawback of a "Only" 256 bit bus for big Navi. this will do incredibly well with Integrated GPU that are even more bandwidth starved. if it's that, this litteraly mean a Jump in integrated GPU performance.

It could also explain why they did more of Vega APU while they were focusing on getting RDNA2 done.

 

[ARF]

the wafts of air an ass puts out

If the moderators don't use double standards, they have to address this personal attack and trolling.

 

[evernessince]

Big If there,

but if the infinity cache help to alleviate the performance drawback of a "Only" 256 bit bus for big Navi. this will do incredibly well with Integrated GPU that are even more bandwidth starved. if it's that, this litteraly mean a Jump in integrated GPU performance.

It could also explain why they did more of Vega APU while they were focusing on getting RDNA2 done.

The more exciting part is the potential for performance improvements it could bring. Yes it could help memory bandwidth but having what is essentially a large L3 cache on the GPU could drastically speed up games. Imagine frequently accessed game engine data that was previously being stored on the VRAM is instead on the infinity cache. You are talking about a massive improvement to latency and bandwidth.

 

[bug]

That die size puts an upper limit on expectations: double the size means double the transistor count (they're both 7FF). Subtract the area for RTRT (Turing used like 20% die area), the rumored increase in cache sizes and you get 75% more CUs, tops. If AMD can put all that to good use, they may be on to something. The downside, as Turing reminded us, is dies that big don't come cheap.

 

[InVasMani]

The more exciting part is the potential for performance improvements it could bring. Yes it could help memory bandwidth but having what is essentially a large L3 cache on the GPU could drastically speed up games. Imagine frequently accessed game engine data that was previously being stored on the VRAM is instead on the infinity cache. You are talking about a massive improvement to latency and bandwidth.

We already saw a bit of this with Intel's desktop Broadwell with the EDRAM, but this appears a bit more advanced. Regardless if true I can defiantly see it hopefully providing a nice impact to 1% and 0.1% percentiles that are latency sensitive. Some of that of course depends on how much can fit into the cache and how it gets allocated.

 

[SIGSEGV]

looks fake.