- Joined
- Jan 3, 2021
- Messages
- 3,843 (2.55/day)
- Location
- Slovenia
Processor | i5-6600K |
---|---|
Motherboard | Asus Z170A |
Cooling | some cheap Cooler Master Hyper 103 or similar |
Memory | 16GB DDR4-2400 |
Video Card(s) | IGP |
Storage | Samsung 850 EVO 250GB |
Display(s) | 2x Oldell 24" 1920x1200 |
Case | Bitfenix Nova white windowless non-mesh |
Audio Device(s) | E-mu 1212m PCI |
Power Supply | Seasonic G-360 |
Mouse | Logitech Marble trackball, never had a mouse |
Keyboard | Key Tronic KT2000, no Win key because 1994 |
Software | Oldwin |
I find it problematic for another reason.The picture you show, where the whole L3 (maybe? including L3-Control, L3-Tags and L2-ShadowTags) are only in the V-Cache-Layer. I find that problematic.
And the area the Zen4c cores take in your picture, again seem not necessary to me in the layout you chose,
because in the Zen3 layout below full equally big cores are placeable easily where the L3 sits normally.
So for me it makes nearly no sense area wise or efficiency wise.
With V-Cache as we know it now, AMD can choose between two variants: a "normal" one-layer package and a "super-cached" two-layer package, considerably more expensive and with a thermal tradeoff. This affords them quite a lot of flexibility. I'm sure each of them will find its place in servers and HPC clusters.
Now with this new proposed configuration, only the latter can exist. That's unless AMD also puts a part of L3 cache, certainly slower, on the I/O die.