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AMD Ryzen 9 7900X CPU-Z Benched, Falls Short of Core i7-12700K in ST, Probably Due to Temperature Throttling

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N4 is old? LOL. Apple has just launched it's first N4 SoC. N3E is planned for A17. Which is still far away. N3E mass production is scheduled for 2H 2023.

What exactly do you think N4 is? Do you think it is 4nm or something? Maybe you should look that up.
 

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I think there was an article on WikiChip or maybe SemiWiki not too long ago (couple of years) showing that N5 and similar nodes was the inflection point for cost, where it began to be more expensive per transistor (aka per chip) to make vs N7 and larger nodes. That does appear to be playing out, anecdotally anyway.

A big part of why the cost of a CPU for example flatlined for 20+ years, despite having more and more transistors and associated fab costs along with normal compounding inflation effects, was the increase in density meant more chips per wafer. If we have hit that inflection point where cost to produce ramps faster than density improvements and per wafer chip yields can offset, then the next 20 years will look quite different than the last 20 years.

If this trend continues, it will naturally tend to harm the markets, and I expect that the businesses will go under. It is not sustainable anymore.

N4 is old? LOL. Apple has just launched it's first N4 SoC. N3E is planned for A17. Which is still far away. N3E mass production is scheduled for 2H 2023.

Well, N4 is in fact N5+, and N5 is which began risk production in 2019.
 
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Mass production of chips tends to start 6-9 months before they come to market though. One thing is that the full production process of a single wafer can take a month or more; another is testing, binning, packaging, etc. Then there's building up sufficient stock before launch, and then there's putting them into whatever products they're going into (unless they're being sold directly). These things take time. But it does indeed seem like N3 has been slated for mass production in "late 2022" for a while now.

Still, N5/N4 are still essentially cutting edge nodes - they're more advanced than what is widely adopted in most industries, and in most high volume chip production. And they're massively expensive still (though hopefully prices are dropping now that TSMC's order numbers are dropping).
You're right that mass production tends to start well before they come to market; still, as there is no product available that uses N3, I think it is fair to regard N4 and N5 as leading nodes.
 

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You're right that mass production tends to start well before they come to market; still, as there is no product available that uses N3, I think it is fair to regard N4 and N5 as leading nodes.

If you look at the production plans, TSMC plans to develop N5/N4 and N3 concurrently, with several different flavours of basically the same node:
N5 N5P N4 N4P N4X 4N
5 nm process - Wikipedia
 
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Yes, it is a completely different story. First, TSMC's N6 will offer significant power savings compared to 12nm Glofo. It doesn't matter if I/O or compute logic. It applies to all transistors. And second, AMD optimized the new IOD for low power. Both combined will result in substantial less power requirements. I wouldn't be surprised if the new IOD can reduce power consumption by about 50%.
Sorry, but no. It's not the transistors that are consuming the power, it's signal power - the power needed to maintain signal integrity through the signal path. More efficient transistors don't meaningfully lower signal power - they can affect it indirectly if they allow for better denoising and overall signal reception, but not directly, and never by a ton. And, as I said, any such improvements are likely to be consumed on their journey towards 3000MHz IF clock speeds to match DDR5. The logic parts of the IOD will of course be more efficient, but that's not the chief power draw of the IOD, and will as such not make a massive difference either.
 
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If you look at the production plans, TSMC plans to develop N5/N4 and N3 concurrently, with several different flavours of basically the same node:
N5 N5P N4 N4P N4X 4N
5 nm process - Wikipedia
That isn't new. TSMC and other fabs make variants of mature processes to satisfy different customers. However, after reading the wikichip article that I linked to earlier, it seems that N3 will be a short-lived node like 20nm before it. However, unlike 20 nm, it is so different from N3E that a design made for N3 won't be portable to N3E. Realistically, N3 may end up being used only by Apple.
 

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That isn't new. TSMC and other fabs make variants of mature processes to satisfy different customers. However, after reading the wikichip article that I linked to earlier, it seems that N3 will be a short-lived node like 20nm before it. However, unlike 20 nm, it is so different from N3E that a design made for N3 won't be portable to N3E. Realistically, N3 may end up being used only by Apple.

I really regret to hear this. Because historically AMD used to be the pioneer on brand new, cutting edge nodes, while today it simply trails behind the competition. N6 node for Navi 3X and IOd, and N5 for all the rest compared to N4 for nvidia doesn't bode well.
 
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Sorry, but no. It's not the transistors that are consuming the power, it's signal power - the power needed to maintain signal integrity through the signal path. More efficient transistors don't meaningfully lower signal power - they can affect it indirectly if they allow for better denoising and overall signal reception, but not directly, and never by a ton. And, as I said, any such improvements are likely to be consumed on their journey towards 3000MHz IF clock speeds to match DDR5. The logic parts of the IOD will of course be more efficient, but that's not the chief power draw of the IOD, and will as such not make a massive difference either.
What are amd and tsmc using for signal wires copper ?
 
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I really regret to hear this. Because historically AMD used to be the pioneer on brand new, cutting edge nodes, while today it simply trails behind the competition. N6 node for Navi 3X and IOd, and N5 for all the rest compared to N4 for nvidia doesn't bode well.
I would no say that they're trailing behind. N5 and N6 are perfectly viable nodes and cheaper than N4. Besides N4 is half shrink of N5 not a full node shrink like N3.
 
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What are amd and tsmc using for signal wires copper ?
AFAIK yes. I don't think there are other good options (though no doubt there's a lot of materials science put into this). It would probably be a good candidate for optical interconnects, but die to die interconnects are far closer to reality than that.
 

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I would no say that they're trailing behind. N5 and N6 are perfectly viable nodes and cheaper than N4. Besides N4 is half shrink of N5 not a full node shrink like N3.

N4 is not a shrink. It is N5+ rebranded for marketing fraud.
 
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N4 is not a shrink. It is N5+ rebranded for marketing fraud.
Lol, "fraud" how exactly? Names are arbitrary. It is a meaningful differentiation as TSMC already has several N5 nodes, and the N4 nodes improve on these in notable ways. Nothing huge, but the changes are real.
 

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Lol, "fraud" how exactly? Names are arbitrary. It is a meaningful differentiation as TSMC already has several N5 nodes, and the N4 nodes improve on these in notable ways. Nothing huge, but the changes are real.

We have been misled for years, claiming that the "nm is actually the minimal feature size of the corresponding manufacturing process".
Which is proved now to be a lie. It is a scam. :banghead:

The worst thing is that there is NO global agreement between the manufacturers on how to label these manufacturing processes.

So, in the end people get Samsung 5LPE/4LPE to be in the range of TSMC N6 process.

"""The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.[14] However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption,[15][16] Moreover, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node. Typically the chip manufacturer refers to its own previous process node (in this case the 5 nm process node) for comparison."""
3 nm process - Wikipedia
 
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We have been misled for years, claiming that the "nm is actually the minimal feature size of the corresponding manufacturing process".
Which is proved now to be a lie. It is a scam. :banghead:

The worst thing is that there is NO global agreement between the manufacturers on how to label these manufacturing processes.

So, in the end people get Samsung 5LPE/4LPE to be in the range of TSMC N6 process.

"""The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.[14] However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption,[15][16] Moreover, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node. Typically the chip manufacturer refers to its own previous process node (in this case the 5 nm process node) for comparison."""
3 nm process - Wikipedia
Yes, this is quite widely known and accepted. As I said: names are arbitrary. My question still stands: why is this a scam? It's a marketing name. The latest TSMC node might as well be named Bob - it doesn't matter. It hasn't been "proved to be a lie" - nobody has claimed this to be a true representation of node feature sizes, not for years and years.

Whether or not it matches a physical feature of the product is utterly irrelevant as long as they're not promising functionality that they can't deliver. That's where calling it a scam falls apart - this isn't selling a 150Hp car engine as being 250Hp, or a 600 lumen light bulb as 1000 lumen. Exact feature sizes of the nodes are utterly and completely irrelevant - it's the performance and characteristics of the node that matters. And the fact that node changes today are smaller than ten or twenty years ago doesn't directly matter to anyone outside of the few thousand chip design engineers in the world - and these people know very, very well what the characteristics of these nodes are. What matters is how actual products perform.

Also: TSMC no longer uses nm or nanometers to designate their nodes, so that part of your argument kind of falls apart, no? They have adopted a fully arbitrary naming scheme that points backwards to previous "XXnm" naming, but makes absolutely zero claims about feature sizes. The same goes for Samsung, and now Intel too. None of this is a scam, as nobody is being promised anything meaningful that they aren't getting. If you feel like you're being promised a 5nm feature size but aren't getting it.... so what? Do you use your chips to actually do things, or are you spending all day looking at them through electron microscopes?

Performance and related traits matter. Feature sizes don't matter outside of how they affect performance and density - and they don't matter at all in an absolute sense, only through how they change things compared to previous and competing nodes.
 

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@Valantar I deeply regret to disagree with you. You are simply wrong.
Yes, the customers do expect some performance, which is not offered by the manufacturer.
For example, how would you explain that "Samsung 3GAE/3GAP" is a crap node in the range of TSMC N4/N4P/N4X and not competitive at all with TSMC' own N3/E nodes which are miles ahead??

Read this:

""OregonLive got a scoop about Intel potentially renaming their 7nm process to 5nm to match the marketing schemes from the foundries. If Intel does this, SemiAccurate feels they are walking into a trap that will accomplish nothing more then making them look worse.
The idea is simple enough, over the past decade or two, process nodes have become completely disentangled from the bonds of reality when it comes to naming. The old micron/nanometer naming convention was based on the smallest line/feature that a node could draw, more or less. Actually lets run with the disclaimer up front, there is a lot of stuff in this article that we will massively oversimplify and some we won’t cover, the broad ideas are what matter, not the technical details. This story is about marketing games that are more or less entirely divorced from anything reality based after all. We will also point out that none of the players in this story have anything close to clean hands.""
Intel should not rename their processes - SemiAccurate
 
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@Valantar I deeply regret to disagree with you. You are simply wrong.
Yes, the customers do expect some performance, which is not offered by the manufacturer.
For example, how would you explain that "Samsung 3GAE/3GAP" is a crap node in the range of TSMC N4/N4P/N4X and not competitive at all with TSMC' own N3/E nodes which are miles ahead??
... and? Is there some universal law saying that things with similar names must perform similarly? Do all cars with 1.6l engines perform the same? Are all 5-seat cars equally roomy? Are all 4-person wooden dining tables of the same quality? Are all 55" TVs equally good? No. Relations between names and characteristics are tenuous at best, and do not in any way fully represent the performance or relevant characteristics of the thing in question, outside of extremely simple things (if you're selling a spoon that can't actually scoop anything up, then calling that a spoon is a problem).

Your second line here perfectly encapsulates the problem with your understanding here. You say "the customer expects some performance" - which is exactly what I'm saying as well. What matters is how the node performs, not what number is on the sticker. Names are arbitrary; performance characteristics are real and meaningful. Customers expect performance increases, and do not care whatsoever about whether or not the smallest feature of the node is actually the same number of nm as the number in the node's name. Why would they care? How would that matter to anyone? Feature sizes in nanometers are not in any way directly related to how a node performs - that's far, far too simplistic - as is aptly demonstrated by the performance differences between different "7nm-class" nodes despite these having relatively well matched feature sizes.

There is literally no reason why names need to have a direct relation to reality. That's not how language works on any level - the representational operations of language are symbolic, not indexical. A name can be literally whatever people agree on it being.
Read this:

""OregonLive got a scoop about Intel potentially renaming their 7nm process to 5nm to match the marketing schemes from the foundries. If Intel does this, SemiAccurate feels they are walking into a trap that will accomplish nothing more then making them look worse.
The idea is simple enough, over the past decade or two, process nodes have become completely disentangled from the bonds of reality when it comes to naming. The old micron/nanometer naming convention was based on the smallest line/feature that a node could draw, more or less. Actually lets run with the disclaimer up front, there is a lot of stuff in this article that we will massively oversimplify and some we won’t cover, the broad ideas are what matter, not the technical details. This story is about marketing games that are more or less entirely divorced from anything reality based after all. We will also point out that none of the players in this story have anything close to clean hands.""
Intel should not rename their processes - SemiAccurate
Yes, the old naming convention was based on this, as that quote says. But this hasn't been reality for, what, a decade now? And the entire industry has abandoned that practice - first implicitly, then explicitly. Is there some reason why they can't change how they name their products?

What that paragraph argues is that Intel shouldn't rename their process nodes because it would make them look bad, as unlike the other actors in the industry they haven't made as gradual of a shift towards a newer scheme - forcing them to explicitly rename nodes that are already launched. You could make a principled argument of some kind here, but then that would need to apply to literally every node created over the past decade - and it wouldn't matter whatsoever, as their performance would still be the same regardless. Whether TSMC N3 is called N3 or "TSMC 22nm interconnect pitch" is entirely irrelevant to its performance, and thus to customers - beyond the latter being complicated and difficult to deal with as a name. The only circumstances in which this would be anywhere close to a scam is if they were promising performance improvements that they aren't delivering.
 

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... and? Is there some universal law saying that things with similar names must perform similarly? Do all cars with 1.6l engines perform the same? Are all 5-seat cars equally roomy? Are all 4-person wooden dining tables of the same quality? Are all 55" TVs equally good? No. Relations between names and characteristics are tenuous at best, and do not in any way fully represent the performance or relevant characteristics of the thing in question, outside of extremely simple things (if you're selling a spoon that can't actually scoop anything up, then calling that a spoon is a problem).

Your second line here perfectly encapsulates the problem with your understanding here. You say "the customer expects some performance" - which is exactly what I'm saying as well. What matters is how the node performs, not what number is on the sticker. Names are arbitrary; performance characteristics are real and meaningful. Customers expect performance increases, and do not care whatsoever about whether or not the smallest feature of the node is actually the same number of nm as the number in the node's name. Why would they care? How would that matter to anyone? Feature sizes in nanometers are not in any way directly related to how a node performs - that's far, far too simplistic - as is aptly demonstrated by the performance differences between different "7nm-class" nodes despite these having relatively well matched feature sizes.

There is literally no reason why names need to have a direct relation to reality. That's not how language works on any level - the representational operations of language are symbolic, not indexical. A name can be literally whatever people agree on it being.

All 1.6l engines should be equal but how will you feel if your car manufacturer decides to call its new 1.0l a "1.6l"? :D
 
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All 1.6l engines should be equal
.... that pretty much sums up the degree of lack of understanding behind your arguments. The point is: designating engines by displacement, just as designating nodes by their smallest feature, is arbitrary. That this is the convention we've landed on is pretty much random - wouldn't horsepower, or some function of efficiency and horsepower be a better grounds for comparison? Yes, obviously. But instead we use a simple number that seems to indicate something, but really doesn't at all. Your 1.6l engine might have 80HP, or 350 - there's no way of knowing if all you have to go by is the displacement. Which means: it's just a name. It's ultimately a shorthand for something vague at best. It doesn't give meaningful promises about anything much at all, just a vague indication in a general direction - just like "lower number on the node is generally better" does. Liters of displacement, just like nm for the smallest feature of a node, does not tell you anything about its performance, save for internal comparisons (a 1.6l Peugeot engine is likely less powerful than a 2.0l Peugeot in the same car; Samsung 8 is likely superior to Samsung 14). That's it, neither more nor less. You're acting as if these numbers give specific indications of performance. They don't, and they never have - that's literally impossible for a short designation for a complex thing.
 
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I would no say that they're trailing behind. N5 and N6 are perfectly viable nodes and cheaper than N4. Besides N4 is half shrink of N5 not a full node shrink like N3.

N4 is not a half node shrink. The density vs N5 is +6%.

What it is, is an improved library on N5. In old intel parlance it would be N5+. Keep in mind these are not nanometers, these are like model numbers.

N3 is a little bit better than a half node shrink vs N5, it is not a full node shrink though. In fact I believe the newer "N3E" is actually less dense than the N3 node, but allows for higher power. i.e. it is a library adjustment again.

1663880961619.png
 
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And, as I said, any such improvements are likely to be consumed on their journey towards 3000MHz IF clock speeds to match DDR5. The logic parts of the IOD will of course be more efficient, but that's not the chief power draw of the IOD, and will as such not make a massive difference either.
Sry, but no. It will make a significant difference. You will see it at launch. ;)

Well, N4 is in fact N5+, and N5 is which began risk production in 2019.
Irrelevant. It's the newest available process from TSMC. It's not old in any way.

N4 is not a half node shrink. The density vs N5 is +6%.
But keep in mind, N4 has not just density advantages. It also offers better performance and less complexity.

 
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Sry, but no. It will make a significant difference. You will see it at launch. ;)
Sure, if anyone at all will do per-core power scaling tests or even any kind of low level power monitoring to differentiate idle power from load power and work out the real uncore power draw. Very, very few reviews come even close to this level of detail. TPU, for example, only reports full system power draw for CPU testing, which obliterates even the most remote possibility of identifying real uncore power draws.

Wrong. N4 is an old process. The newest is N3 and the largest customer Apple has already begun mass production. Risk production commenced many months ago:

View attachment 262941
3nm Technology - Taiwan Semiconductor Manufacturing Company Limited (tsmc.com)
Except that risk production is not mass production, there can be major gaps between the two, and there are major scaling factors even after mass production is started, with production 6-12 months after the start of HVM often being 5-10x higher. And, of course, calling a process node that entered mass production this year "old" is downright ridiculous, especially given the long-running and still ongoing slowdown of process node improvements. N3 has at best just started HVM, which means that volumes are still very low, likely too low for them to produce chips for anyone but the single highest paying customer, Apple.
 

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Except that risk production is not mass production, there can be major gaps between the two, and there are major scaling factors even after mass production is started, with production 6-12 months after the start of HVM often being 5-10x higher. And, of course, calling a process node that entered mass production this year "old" is downright ridiculous, especially given the long-running and still ongoing slowdown of process node improvements. N3 has at best just started HVM, which means that volumes are still very low, likely too low for them to produce chips for anyone but the single highest paying customer, Apple.

Nothing stopped nvidia to postpone the RTX 4000 series launch by several months and make it on the far superior N3 process instead.
But nvidia is run by lunatics, while AMD is run by lazy who will lag behind until 2025.
 
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Nothing stopped nvidia to postpone the RTX 4000 series launch by several months and make it on the far superior N3 process instead.
But nvidia is run by lunatics, while AMD is run by lazy who will lag behind until 2025.
"Several months"? How long, exactly, do you think the processing of a single wafer takes, and how long, exactly, do you think it will take for TSMC's 3nm production capacity to surpass Apple's orders? And, crucially, how long do you think it takes to build up sufficient stock of a new chip to ship to AIB partners that can then make it into a sufficient amount of GPUs for a retail launch?

Let's be extremely generous and assume the N3 "H2 2022" date means July 1st. And let's be even more absurdly generous and say it took TSMC three months to have significant spare N3 capacity that Apple either didn't want or didn't have an option to buy first. That would place the start of GPU die mass production on October 1st. Processing a single wafer takes ~1 month (a bit less on some processes, more on others). Let's assume TSMC had 10 000 wafer starts/month of free N3 capacity (which is likely closer to their total N3 capacity that early), and that they all went into producing a 3nm AD102. Assuming perfect scaling, that would be a ~375mm2 die (using scaling numbers from here). Let's assume the chip is a bit rectangular, something like 15*25mm. Assuming the "N7 standard" 0.09 defects/cm2 - which is again highly unlikely this early in mass production of a new node, and thus a very generous assumption - and plugging those numbers into a wafer yield calculator, that gives us 101 good dice per wafer, and 39 defective dice, the majority of which can likely be used for a cut-down SKU. Let's say they get 130 RTX 4090-capable dice out of each wafer. That gives us 1.3M GPU dice after a month of production. Which sounds like a lot! Except that every single assumption made in this calculation is wildly unrealistic.
- Apple most likely has 6 months or more exclusive access to N3 mass production, and past any exclusivity period they will have first purchasing rights to any spare capacity
- Even disregarding that, there is no way there are 10 000 available wafer starts after three months for Nvidia - 10% of that is more likely, if not even less.
- This all assumes that the chip is already fully taped out and has had test production runs so that the ramp to mass production is smooth.
- N3 yields are likely significantly lower than 0.09 defects/cm2 this early in mass production.

And, crucially, the die being done doesn't mean it's ready to go on shelves - the wafers need to be shipped to a packaging plant where the wafer is cut, the dice are tested, binned and packaged. The packaged dice are then sold and shipped on to AIB partners, who - again, assuming they've had sufficient access to ES silicon - will then ramp mass production of GPU PCBs and coolers (some of this might be made ahead of time, but these companies generally don't have the cash flow to keep significant parts stock for long periods of time). Then the finished GPUs need to go through QC, testing and retail packaging, before being shipped to distribution centers and then shipped across the globe. This is, at best, a 4-6 month process from a wafer starts processing till the finished product reaches retail shelves. Assuming everything goes smoothly. So, even with wildly unrealistic base assumptions, Nvidia would in a best case scenario be able to launch the 4000 series on N3 somewhere in the early February - late March 2023 timeframe. With any kind of realistic assumptions, we'd be talking H2 2023, if not later. That's a full year's delay, not "several months".
 
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