AMD Ryzen 9 9950X3D Carries 3D V-Cache on a Single CCD, 5.6 GHz Clock Speed, and 170 Watt TDP

[Random_User]

For the people who keep quoting Latency graphs to argue there is no penalty, consider this. Those tests you are quoting are 1 core accessing 1 core on the 2nd CCD, I have linked a test that goes into further details where they load down CCDS from single thread to fully loaded and measured its latency and in actually splitting threads across the two CCDs and with Zen 4 it is bad!!!

Pushing AMD’s Infinity Fabric to its Limits

I recently wrote code to test memory latency under load, seeking to reproduce data in various presentations with bandwidth on the X axis and latency on the Y axis.

chipsandcheese.com

Zen 4 has a hardware limitation that a dual X3D setup would have been absolutly HORRENDOUS in performance as accessing the 2nd CCDs cache would have been only as fast as accessing DRAM in certain worst case scenarios and can very easily see 2-3 times the latency penalty rising to nearly 10 times in the worst case. I suspect Zen 3/5xxx series parts would have seen similar issues due to the design of the IO Die etc

Zen 5 has seemingly fixed this issue as well as having the high clock speeds due to the relocated X3D. I wonder if we AMD are holding back dual X3D parts in case Intel pulls something out of the bag ala Nvidias origianl Ti/Super variants of a few years ago? I mean the Single CCD parts are completely handing Intel the L in gaming by quite a margin currently.

Also are they trying to prevent confusion as the dual x3d parts would segregate the market even futher again as you now have 3 different SKUs for each core count and with desktop parts probably pushing up towards the $/£1k mark again for the top end non HEDT part. How much would it cut into their lower end HEDT/Workstation sales.

My bet, is that this is just the margin/business thing. They want to milk with limited SKU, for as long as possible. This is "reasonable" from the business standpoint, but atrocious, from every other. Including amount of e-waste, produced for the sole purpose of very temporary sales boost, while intel has nothing on the table, yet. As these heterohgenous SKUs might be as avoided, as Zen4 ones, despite they could be a solid solution from the get go. These hybrid stuff might be eclipsed and avoided again in favor of either mono-3D, single 9800X3D, or any ppotential dual CCD 3D. Money...

 

[junglist724]

Sigh.... Still with the assymentric cache arrangement....

Was kind of hoping they would do that as a 'lower' tier Ryzen 9 part and release a dual-CCD X3D top-tier Ryzen 9 CPU....

It's a pain having to use windows gamebar or set process affinity but if a game is crossing CCDs that latency penalty is so huge the vcache won't matter anyways.

 

[A&P211]

What they really need is OS support so programmers can manually assign threads to the CCD of choice. Each CCD in the non-x3d cache version already had a massive cache and dividing workloads among CCD's can be a significant boost at the application level when the application doesn't need all cores.

Saving 20 seconds on compile is another 20 seconds to sip coffee. (No joke.)

For me, its 20 more sec of TPU, watching porn, then green tea, all in that order.

 

[Wirko]

For me, its 20 more sec of TPU, watching porn, then green tea, all in that order.

None of these activities should be rationed by the second but to each his own.