AMD Zen 5 Technical Deep Dive

[Cifu]

...the highest stable memory speed you can achieve with a 1:1 parity between the FCLK and MCLK clock domains....

Emmm... no, UCLK = MCLK, other name: Gear1.
The FCLK are totally unbound to the UCLK / MCLK (just as the Zen4 Raphael case).

 

[Dr. Dro]

Someone please get their CPU team to work on Radeon for a generation or two...

 

[sodium]

Idle and low load power consumption will be terrible as long as the I/O die is still there sucking power.

 

[vgm]

@W1zzard Just a typo in the first image should be "Unveiled". Ryzen 9000 Unvealed
Just watched Gamers Nexus and AMD's OC and WR numbers. Would love to see curve shaper's usage and power efficiency against Space Heaters certified for use in client machines.
AMD needs to bring undervolt to laptops.

 

[Jism]

The high core voltage was described as intentionally excessive, to ensure the demos could proceed in a reasonable time, without lots of reboots to find the sweet spot voltage.

Can we get a moment of silence for the fallen soldier?

 

[Cheeseball]

Ahh yes. Getting more performance from a fixed 15W TDP setting is important, especially for gaming handhelds and tablets. Sadly, it doesn't look like we can reach lower Steam Deck TDP levels (<15W) due to the extra 4 or 6 cores still needing a bit of power even if they're parked/disabled.

They really should've made the Z1 non-Extreme a 6-core, 8 CU part. Essentially a rebadged 7640U/8640U/8600G.

 

[Lianna]

Whoever started recently calling Zen4-style AVX512 implementation "double-pumped" should feel ashamed.
"Double-pumped" referred to execution units doing twice the work in one cycle (two dependent uops), e.g. P4 simple ALU units.
Execution units in Zen 4 are clocked the same for both AVX2 and AVX512, they just work together (or sequentially) on two halves of the operand for AVX512.
This type of execution, since P4 (2x64bit then) was called "combining" or "joining" high/low part (half) operations and, depending on implementation, either "staggered"/"dual-cycle" (P4/PM) or "two ports fused together" (Skylake-X, ports 0 and 1) or "execution unit teaming" or "implemented with 256-bit operations" (Zen 4).

 

[mkppo]

Huh?

This is a typo (and contradicted on the very next page).

AMD Ryzen 7840U
Launched May 2023
NPU: 10 TOPs

Intel Meteor Lake
Launched December 2023
NPU: 9.5 TOPs

AMD launched first and still has the fastest NPU in any x86 SoC. Intel is playing catch-up. And both Intel & AMD are playing catch up with Apple's ANE since the late 2020 M1.

That's what I was wondering when I read the article..

The CPU arch itself looks to be heavy on the front end. I'd wager a guess and say it will scale extremely well with memory overclocking/latency improvements as that's where the bottleneck seems to be at

It should also scale better with power than the 7950x, there's just more to power in the arch..Not saying efficiency will be worse than previous gen, far from it, but it'll scale past where the 7950x capped at (roughly 210W for the 7950 IIRC)

 

[KaitouX]

The Handbrake numbers are really weird, in particular that 94%+ over the 14600K on the 9600X slide is bizarre. Is there any mention on what exactly was used on Handbrake? The notes seems to only say Handbrake too.
Even the worst case scenario for the 14600K that I'm aware which would be the SVT-AV1 using AVX512 on Ryzen, the 9600X shouldn't be nowhere near that number, as even in that case the 14600K was over 20% faster than the 7600X.

 

[Chrispy_]

Why does the B840 even exist?

Gen3 graphics has been a huge problem at the low-end with crappy PCIe 4.0 x4 and x8 GPUs that chop off lanes to save money, cutting 10-40% off the potential performance in a very price and performance-sensitive market segment.

AMD is offering ancient PCIe 3.0 chipsets to the exact market that needs to move away from Gen3 the most.

/smh

 

[jesdals]

Is it 64MB cache for the 9950 or 80 as mentioned in the AMD slides?

 

[dir_d]

Why does the B840 even exist?

Gen3 graphics has been a huge problem at the low-end with crappy PCIe 4.0 x4 and x8 GPUs that chop off lanes to save money, cutting 10-40% off the potential performance in a very price and performance-sensitive market segment.

AMD is offering ancient PCIe 3.0 chipsets to the exact market that needs to move away from Gen3 the most.

/smh

I would say the chipset is for business machines in corporate offices.

 

[GenericUsername2001]

View attachment 355247

Ahh yes. Getting more performance from a fixed 15W TDP setting is important, especially for gaming handhelds and tablets. Sadly, it doesn't look like we can reach lower Steam Deck TDP levels (<15W) due to the extra 4 or 6 cores still needing a bit of power even if they're parked/disabled.

They really should've made the Z1 non-Extreme a 6-core, 8 CU part. Essentially a rebadged 7640U/8640U/8600G.

AMD has Kracken Point coming out early 2025, which will be an 8 core (4 regular, 4c), 8 CU part, intended for more budget laptops; it will probably also end up in those gaming handhelds & tablets.

 

[sLowEnd]

Why does the B840 even exist?

Gen3 graphics has been a huge problem at the low-end with crappy PCIe 4.0 x4 and x8 GPUs that chop off lanes to save money, cutting 10-40% off the potential performance in a very price and performance-sensitive market segment.

AMD is offering ancient PCIe 3.0 chipsets to the exact market that needs to move away from Gen3 the most.

/smh

It's probably for systems that will stick to iGPUs. It'd better be damn cheap to have any appeal though.

I find it weird that AMD places it against the B760 on their slide, when it seems more like an H610 competitor feature-wise.

 

[mkppo]

Is it 64MB cache for the 9950 or 80 as mentioned in the AMD slides?

64 L3, 16MB L2 for 80 total as before

 

[EatingDirt]

Idle and low load power consumption will be terrible as long as the I/O die is still there sucking power.

Intel CPU's also have an IO die sucking power. That's just how modern platforms work.

That being said, in low load (single threaded) workloads the 7950x takes a whole 6w more(41w) than the 14900k(37w). That's going to add up to probably less than $10 a year, and that's if your energy costs are on the +$0.40 USD range(very high).

Over the lifetime of the CPU it's an insignificant difference, one that evens out if you ever run the CPU higher than... well, practically idle(Zen is typically more efficient than Intel at higher loads).

 

[Dr. Dro]

Intel CPU's also have an IO die sucking power. That's just how modern platforms work.

?? No, they do not. Desktop Intel chips are fully monolithic at the moment.

 

[R0H1T]

He probably meant the upcoming ARL & that would be a great point of reference for AMD.

 

[Steevo]

?? No, they do not. Desktop Intel chips are fully monolithic at the moment.

Still use the same power and Intel high end are dying currently due to Intels own TVB…

AMD can pull off a win if they release these with no day one issues.

 

[Dr. Dro]

Still use the same power and Intel high end are dying currently due to Intels own TVB…

AMD can pull off a win if they release these with no day one issues.

The eTVB issue is separate and is not why the chips are dying... but no, AMD idle power has been several times that of Intel because they are monolithic chips. This is the same reason the APUs have lower idle power, no IOD to constantly draw power. Zen 5 is great, but this is clearly not something it has addressed thus far. AMD likely cannot address it, at least not with a cost-effective solution yet.

 

[Chrispy_]

I would say the chipset is for business machines in corporate offices.

Business machines in corporate offices are Intel N100 thin-clients. AMD doesn't have a presence in that sector.

 

[Visible Noise]

Did anyone else notice PBO isn’t available on 9950?

Based on those slides the 9700x seems to be quite power constrained. The gain in performance is only half of the 9950x while PBO shows a gain twice as big as the other Zen 5 CPUs.

Look at what they did to the base clocks. That’s one way to market a lower TDP.